參數(shù)資料
型號(hào)： AD5380BST-3
廠商： ANALOG DEVICES INC
元件分類： DAC
英文描述： 40-Channel, 3V/5V Single Supply, 14-Bit, Voltage-Output DAC
中文描述： PARALLEL, WORD INPUT LOADING, 8 us SETTLING TIME, 14-BIT DAC, PQFP100
封裝： 14 X 14 MM, MS-026BED, LQFP-100
文件頁(yè)數(shù)： 23/34頁(yè)
文件大?。?/td> 975K
代理商： AD5380BST-3
PRELIMINARY TECHNICAL DATA
REV. PrF 09/2003
AD5380
–23–
Power-On-Reset
The AD5380 contains a power-on-reset generator and state-machine. The power-on-reset resets all registers to a
predefined state and the analog outputs are configured with a 100k impedance to ground. The
BUSY
pin goes low
during the power-on-reset sequencing preventing data writes to the device.
Power-Down
The AD5380 contains a global power-down feature that puts all channels into a low power mode reducing both analog
and digital power consumption to 5uA. In power down mode the output amplifier can be configured as a high impedance
output or provide a 100k load to ground. The contents of all internal registers are retained in power-down mode. When
exiting power down the settling time of the amplifier will elapse before the outputs settle to their correct value.
AD5380 INTERFACES
The AD5380 contains both a parallel and serial interfaces. Furthermore, the serial interface can be programmed to be
either DSP,SPI,MICROWIRE or I2C compatible. The SER/
PAR
pin selects parallel and serial interface modes. In
serial mode SPI/
I2C
pin is used to select DSP,SPI,MICROWIRE or I2C interface mode.
The devices use an internal FIFO memory to allow high speed successive writes in parallel interface mode. The user can
continue writing new data to the device while write instructions are being executed. The
BUSY
signal indicates the
current status of the device, going low while instructions in the FIFO are being executed. Up to 128 successive
intructions can be written to the FIFO at maximum speed in parallel mode. When the FIFO is full any further writes to
the device are ignored.
To minimize both the power consumption of the device and on-chip digital noise, the active interface only powers up
fully when the device is being written to, i.e. on the falling edge of
WR
or on the falling edge of
SYNC
.
DSP, SPI, MICROWIRE COMPATIBLE SERIAL INTERFACES
The serial interface can be operated with a minimum of 3-wires in stand alone mode or 4-wires in daisy chain mode.
Daisy chaining allows many devices to be cascaded together to increase system channel count.The SER/
PAR
pin must be
tied high and the SPI/
I2C
(pin 97) should be tied high to enable the DSP,SPI,MICROWIRE compatible serial
interface. In serial interface mode the user does not need to drive the parallel input data pins. The serial interface is
control pins are as follows:
SYNC
, DIN, SCLK
- Standard 3-wire interface pins.
DCEN
- Selects Stand-Alone Mode or Daisy-Chain Mode.
SDO
- Data Out pin for Daisy-Chain Mode.
Figures 3 and 4 show the timing diagram for a serial write to the AD5380 in both Stand-Alone and Daisy-Chain Mode.
The 24-bit data word format for the serial interface in shown in Figure 9 below.
MSB
LSB
A
/B R/
W
A5 A4 A3 A2
A1 A0
REG1 REG0
DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5
DB4
DB3
DB2 DB1 DB0
Figure 9 . AD5380, 40-Channel, 14-Bit DAC Serial Input Register Configuration
A
/B When Toggle mode is enabled this selects whether the data write is to the A or B register, with Toggle disabled this
bit should be set to zero to select the A data register.
R/
W
is the Read or Write control bit.
A5-A0 are used to Address the input channels .
REG1 & REG0 Select the register to which data is written as outlined in Table 1.
DB13-DB0 Contain the input data word.
X is a dont care condition.
Stand-Alone Mode
By connecting DCEN (Daisy-Chain Enable) pin low, Stand-Alone Mode is enabled. The serial interface works with
both a continuous and a noncontinuous serial clock. The first falling edge of
SYNC
starts the write cycle and resets a
counter that counts the number of serial clocks to ensure that the correct number of bits are shifted into the serial shift
register. Any further edges on
SYNC
except for a falling edge are ignored until 24 bits are clocked in. Once 24 bits
have been shifted in, the SCLK is ignored. In order for another serial transfer to take place the counter must be reset by
the falling edge of
SYNC
.
Daisy-Chain Mode
For systems which contain several devices the SDO pin may be used to daisy-chain several devices together. This daisy-
chain mode can be useful in system diagnostics and reducing the number of serial interface lines.
By connecting DCEN (Daisy-Chain Enable) pin high, the Daisy-Chain Mode is enabled. The first falling edge of
SYNC
starts the write cycle. The SCLK is continuously applied to the input shift register when
SYNC
is low. If more than 24
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