參數(shù)資料
型號: AD5378ABCZ
廠商: Analog Devices Inc
文件頁數(shù): 7/29頁
文件大?。?/td> 0K
描述: IC DAC 14BIT 32CHAN 108CSPBGA
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝: 1
設(shè)置時(shí)間: 20µs
位數(shù): 14
數(shù)據(jù)接口: 串行,并聯(lián)
轉(zhuǎn)換器數(shù)目: 32
電壓電源: 模擬和數(shù)字,雙 ±
功率耗散(最大): 850mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 108-BGA,CSPBGA
供應(yīng)商設(shè)備封裝: 108-CSPBGA(13x13)
包裝: 托盤
輸出數(shù)目和類型: 32 電壓,雙極
采樣率(每秒): 50k
AD5378
Rev. A | Page 14 of 28
Pin
Description
FIFOEN
FIFO Enable. Level sensitive, active high. When connected to DVDD, the internal FIFO is enabled, allowing the user to
write to the device at full speed. FIFO is available in both serial and parallel modes. The FIFOEN pin has an internal
1 MΩ pull-down resistor connected to ground, meaning that the FIFO is disabled by default.
RESET
Asynchronous Digital Reset Input. Falling edge sensitive. If unused, RESET can be left unconnected; an internal pull-up
resistor (1 MΩ) ensures that the RESET input is held high. The function of this pin is equivalent to that of the power-on
reset generator. When this pin is taken low, the AD5378 state machine initiates a reset sequence to digitally reset the
x1, m, c, and x2 registers to their default power-on values. This sequence takes 100 μs (typ). Furthermore, the input to
each of the DAC output buffer stages, VOUT0 to VOUT31, is switched to the externally set potential on the relevant
REFGND pin. During RESET, BUSY goes low and the parallel interface is disabled. All LDAC pulses are ignored until
BUSY goes high. When RESET goes high again, the DAC ouputs remain at REFGND until LDAC is taken low.
REFGNDA1
Reference Ground for DACs 0 to 5. VOUT0 to VOUT5 are referenced to this voltage.
REFGNDA2
Reference Ground for DACs 6 and 7. VOUT6 and VOUT7 are referenced to this voltage.
REFGNDB1
Reference Ground for DACs 8 to 13. VOUT8 to VOUT13 are referenced to this voltage.
REFGNDB2
Reference Ground for DACs 14 and 15. VOUT14 and VOUT15 are referenced to this voltage.
REFGNDC1
Reference Ground for DACs 16 to 21. VOUT16 to VOUT21 are referenced to this voltage.
REFGNDC2
Reference Ground for DACs 22 and 23. VOUT22 and VOUT23 are referenced to this voltage.
REFGNDD1
Reference Ground for DACs 24 to 29. VOUT24 to VOUT29 are referenced to this voltage.
REFGNDD2
Reference Ground for DACs 30 and 31. VOUT30 and VOUT31 are referenced to this voltage.
1 These serial interface signals do not require separate pins, but share parallel interface pins.
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