- 鎮ㄧ従(xi脿n)鍦ㄧ殑浣嶇疆锛�璨疯常IC缍�(w菐ng) > PDF鐩寗9426 > AD5280BRUZ20 (Analog Devices Inc)IC DGTL POT 15V 20K 14-TSSOP PDF璩囨枡涓嬭級
鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | AD5280BRUZ20 |
| 寤犲晢锛� | Analog Devices Inc |
| 鏂囦欢闋佹暩(sh霉)锛� | 8/28闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC DGTL POT 15V 20K 14-TSSOP |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 96 |
| 鎺ョ墖锛� | 256 |
| 闆婚樆锛堟瓙濮嗭級锛� | 20k |
| 闆昏矾鏁�(sh霉)锛� | 1 |
| 婧害绯绘暩(sh霉)锛� | 妯�(bi膩o)婧�(zh菙n)鍊� 30 ppm/°C |
| 瀛樺劜鍣ㄩ鍨嬶細 | 鏄撳け |
| 鎺ュ彛锛� | I²C锛堣ō(sh猫)鍌欎綅鍧€锛� |
| 闆绘簮闆诲锛� | 4.5 V ~ 16.5 V锛�±4.5 V ~ 5.5 V |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 14-TSSOP锛�0.173"锛�4.40mm 瀵級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 14-TSSOP |
| 鍖呰锛� | 绠′欢 |
| 鐢�(ch菐n)鍝佺洰閷勯爜闈細 | 787 (CN2011-ZH PDF) |
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AD5280/AD5282
Rev. C | Page 16 of
28
DIGITAL INTERFACE
2-WIRE SERIAL BUS
The AD5280/AD5282 are controlled via an I2C-compatible serial
bus. The RDACs are connected to this bus as slave devices. As
AD5280/AD5282 is a slave address byte. It has a 7-bit slave
address and an R/W bit.
The 5 MSBs are 01011, and the two bits that follow are deter-
mined by the state of the AD0 pin and the AD1 pin of the
device. AD0 and AD1 allow the user to place up to four of the
I2C-compatible devices on one bus. The 2-wire I2C serial bus
protocol operates as follows.
The master initiates data transfer by establishing a start condi-
tion, which happens when a high-to-low transition on the SDA
line occurs while SCL is high (see Figure 45). The following
byte is the slave address byte, which consists of the 7-bit slave
address followed by an R/W bit (this bit determines whether
data is read from or written to the slave device).
The slave whose address corresponds to the transmitted address
responds by pulling the SDA line low during the ninth clock
pulse (this is called the acknowledge bit). At this stage, all other
devices on the bus remain idle while the selected device waits for
data to be written to or read from its serial register. If the R/W bit
is high, the master reads from the slave device. On the other
hand, if the R/W bit is low, the master writes to the slave device.
A write operation contains one instruction byte more than a
read operation. Such an instruction byte in write mode follows
the slave address byte. The most significant bit (MSB) of the
instruction byte labeled A/B is the RDAC subaddress select. A
low selects RDAC1 and a high selects RDAC2 for the dual
channel AD5282. Set A/B low for the AD5280.
RS, the second MSB, is the midscale reset. A logic high on this
bit moves the wiper of a selected channel to the center tap
where RWA = RWB. This feature effectively writes over the
contents of the register and thus, when taken out of reset mode,
the RDAC remains at midscale.
SD, the third MSB, is a shutdown bit. A logic high causes the
selected channel to open circuit at Terminal A while shorting
the wiper to Terminal B. This operation yields almost 0 惟 in
rheostat mode or 0 V in potentiometer mode. This SD bit serves
the same function as the SHDN pin except that the SHDN pin
reacts to active low. Also, the SHDN pin affects both channels
(AD5282) as opposed to the SD bit, which affects only the
channel that is being written to. Note that the shutdown
operation does not disturb the contents of the register. When
brought out of shutdown, the previous setting is applied to
the RDAC.
The following two bits are O1 and O2. They are extra program-
mable logic outputs that can be used to drive other digital loads,
logic gates, LED drivers, analog switches, and so on. The three
LSBs are don鈥檛 care bits (see Figure 45).
After acknowledging the instruction byte, the last byte in write
mode is the data byte. Data is transmitted over the serial bus in
sequences of nine clock pulses (eight data bits followed by an
acknowledge bit). The transitions on the SDA line must occur
during the low period of SCL and remain stable during the high
period of SCL (see Figure 45).
In read mode, the data byte follows immediately after the
acknowledgment of the slave address byte. Data is transmitted
over the serial bus in sequences of nine clock pulses (a slight
difference from write mode, where there are eight data bits
followed by an acknowledge bit). Similarly, the transitions on
the SDA line must occur during the low period of SCL and
remain stable during the high period of SCL (see Figure 46).
When all data bits have been read or written, a stop condition is
established by the master. A stop condition is defined as a low-
to-high transition on the SDA line while SCL is high. In write
mode, the master pulls the SDA line high during the tenth clock
pulse to establish a stop condition (see Figure 45). In read
mode, the master issues a no acknowledge for the ninth clock
pulse (that is, the SDA line remains high). The master then
brings the SDA line low before the 10th clock pulse, which goes
high to establish a stop condition (see Figure 46).
A repeated write function gives the user flexibility to update the
RDAC output a number of times after addressing and instructing
the part only once. During the write cycle, each data byte updates
the RDAC output. For example, after the RDAC has acknow-
ledged its slave address and instruction bytes, the RDAC output
updates after these two bytes. If another byte is written to the
RDAC while it is still addressed to a specific slave device with the
same instruction, this byte updates the output of the selected slave
device. If different instructions are needed, the write mode has to
start with a new slave address, instruction, and data byte again.
Similarly, a repeated read function of RDAC is also allowed.
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鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| AD5280BRUZ20 | 鍒堕€犲晢:Analog Devices 鍔熻兘鎻忚堪:IC 8-BIT DIGITAL POT |
| AD5280BRUZ200 | 鍔熻兘鎻忚堪:IC DGTL POT 200K 256POS 14-TSSOP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 鏁�(sh霉)瀛楅浕浣嶅櫒 绯诲垪:- 妯�(bi膩o)婧�(zh菙n)鍖呰:3,300 绯诲垪:WiperLock™ 鎺ョ墖:257 闆婚樆锛堟瓙濮嗭級:100k 闆昏矾鏁�(sh霉):1 婧害绯绘暩(sh霉):妯�(bi膩o)婧�(zh菙n)鍊� 150 ppm/°C 瀛樺劜鍣ㄩ鍨�:鏄撳け 鎺ュ彛:3 绶� SPI锛堣姱鐗囬伕鎿囷級 闆绘簮闆诲:1.8 V ~ 5.5 V 宸ヤ綔婧害:-40°C ~ 125°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:8-VDFN 瑁搁湶鐒婄洡 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:8-DFN-EP锛�3x3锛� 鍖呰:甯跺嵎 (TR) |
| AD5280BRUZ2002 | 鍒堕€犲晢:AD 鍒堕€犲晢鍏ㄧū:Analog Devices 鍔熻兘鎻忚堪:Single/Dual,15 V/5 V,256-Position I2C-Compatible Digital Potentiometer |
| AD5280BRUZ200-R7 | 鍔熻兘鎻忚堪:IC POT DGTL 200K 256POS 14TSSOP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 鏁�(sh霉)瀛楅浕浣嶅櫒 绯诲垪:- 妯�(bi膩o)婧�(zh菙n)鍖呰:3,000 绯诲垪:DPP 鎺ョ墖:32 闆婚樆锛堟瓙濮嗭級:10k 闆昏矾鏁�(sh霉):1 婧害绯绘暩(sh霉):妯�(bi膩o)婧�(zh菙n)鍊� 300 ppm/°C 瀛樺劜鍣ㄩ鍨�:闈炴槗澶� 鎺ュ彛:3 绶氫覆琛岋紙鑺墖閬告搰锛岄仦澧烇紝澧�/娓涳級 闆绘簮闆诲:2.5 V ~ 6 V 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:8-WFDFN 瑁搁湶鐒婄洡 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:8-TDFN锛�2x3锛� 鍖呰:甯跺嵎 (TR) |
| AD5280BRUZ200-R72 | 鍒堕€犲晢:AD 鍒堕€犲晢鍏ㄧū:Analog Devices 鍔熻兘鎻忚堪:Single/Dual,15 V/5 V,256-Position I2C-Compatible Digital Potentiometer |
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