AD5280/AD5282
Rev. C | Page 19 of
28
LAYOUT AND POWER SUPPLY BYPASSING
It is a good practice to design a layout with compact, minimum
lead lengths. The leads to the input should be as direct as possible
with a minimum conductor length. Ground paths should have
low resistance and low inductance.
AD5280/
AD5282
VDD
VSS
VDD
VSS
GND
C3
10F
C1
0.1F
C4
10F
C2
0.1F
+
02
92
9-
05
4
Similarly, it is also a good practice to bypass the power supplies
with quality capacitors for optimum stability. Supply leads to
the device should be bypassed with 0.01 μF to 0.1 μF disc or
chip ceramic capacitors. Low ESR 1 μF to 10 μF tantalum or
electrolytic capacitors should also be applied at the supplies to
minimize any transient disturbance and filter low frequency
ripple (see
Figure 54). Notice that the digital ground should also
be joined remotely to the analog ground at one point to
minimize digital ground bounce.
Figure 54. Power Supply Bypassing