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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | AD5280BRUZ20 |
| 寤犲晢锛� | Analog Devices Inc |
| 鏂囦欢闋佹暩(sh霉)锛� | 23/28闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC DGTL POT 15V 20K 14-TSSOP |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 96 |
| 鎺ョ墖锛� | 256 |
| 闆婚樆锛堟瓙濮嗭級锛� | 20k |
| 闆昏矾鏁�(sh霉)锛� | 1 |
| 婧害绯绘暩(sh霉)锛� | 妯�(bi膩o)婧�(zh菙n)鍊� 30 ppm/°C |
| 瀛樺劜(ch菙)鍣ㄩ鍨嬶細 | 鏄撳け |
| 鎺ュ彛锛� | I²C锛堣ō(sh猫)鍌欎綅鍧€锛� |
| 闆绘簮闆诲锛� | 4.5 V ~ 16.5 V锛�±4.5 V ~ 5.5 V |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 14-TSSOP锛�0.173"锛�4.40mm 瀵級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 14-TSSOP |
| 鍖呰锛� | 绠′欢 |
| 鐢�(ch菐n)鍝佺洰閷勯爜闈細 | 787 (CN2011-ZH PDF) |
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AD5280/AD5282
Rev. C | Page 4 of
28
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
Total Harmonic Distortion
THDW
VA = 1 V rms, RAB = 20 k惟
0.014
%
VB = 0 V dc, f = 1 kHz
VW Settling Time
tS
VA = 5 V, VB = 5 V, 卤1 LSB error band
5
渭s
Crosstalk
CT
VA = VDD, VB = 0 V, measure VW1 with
adjacent RDAC making full-scale
code change
15
nV-s
Analog Crosstalk
CTA
Measure VW1 with VW2 = 5 V p-p @ f =
10 kHz
62
dB
Resistor Noise Voltage
eN_WB
RWB = 20 k惟, f = 1 kHz
18
nV/鈭欻z
SCL Clock Frequency
fSCL
0
400
kHz
tBUF Bus Free Time Between
Stop and Start
t1
1.3
渭s
tHD:STA Hold Time (Repeated
Start)
t2
After this period, the first clock pulse
is generated
0.6
渭s
tLOW Low Period of SCL Clock
t3
1.3
渭s
tHIGH High Period of SCL Clock
t4
0.6
渭s
tSU:STA Setup Time for Start
Condition
t5
0.6
渭s
tHD:DAT Data Hold Time
t6
0
0.9
渭s
tSU:DAT Data Setup Time
t7
100
ns
tF Fall Time of Both SDA and
SCL Signals
t8
300
ns
tR Rise Time of Both SDA and
SCL Signals
t9
300
ns
tSU:STO Setup Time for STOP
Condition
t10
0.6
渭s
02
92
9-
0
42
1 Typicals represent average readings at 25掳C, VDD = +5 V, VSS = 5 V.
2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3 VAB = VDD, wiper (VW) = no connect.
4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits
of 卤1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor Terminal A, Resistor Terminal B, and Wiper Terminal W have no limitations on polarity with respect to each other.
6 Guaranteed by design and not subject to production test.
7 PDISS is calculated from (IDD 脳 VDD). CMOS logic level inputs result in minimum power dissipation.
8 Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest
bandwidth. The highest R value results in the minimum overall power consumption.
9 All dynamic characteristics use VDD = 5 V.
10 See timing diagram (Figure 3) for location of measured values.
11 Standard I2C mode operation is guaranteed by design.
t1
t2
t3
t8
t9
t6
t4
t7
t5
t2
t10
PS
S
SCL
SDA
P
Figure 3. Detailed Timing Diagram
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鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
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|---|---|
| AD5280BRUZ20 | 鍒堕€犲晢:Analog Devices 鍔熻兘鎻忚堪:IC 8-BIT DIGITAL POT |
| AD5280BRUZ200 | 鍔熻兘鎻忚堪:IC DGTL POT 200K 256POS 14-TSSOP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 鏁�(sh霉)瀛楅浕浣嶅櫒 绯诲垪:- 妯�(bi膩o)婧�(zh菙n)鍖呰:3,300 绯诲垪:WiperLock™ 鎺ョ墖:257 闆婚樆锛堟瓙濮嗭級:100k 闆昏矾鏁�(sh霉):1 婧害绯绘暩(sh霉):妯�(bi膩o)婧�(zh菙n)鍊� 150 ppm/°C 瀛樺劜(ch菙)鍣ㄩ鍨�:鏄撳け 鎺ュ彛:3 绶� SPI锛堣姱鐗囬伕鎿囷級 闆绘簮闆诲:1.8 V ~ 5.5 V 宸ヤ綔婧害:-40°C ~ 125°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:8-VDFN 瑁搁湶鐒婄洡 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:8-DFN-EP锛�3x3锛� 鍖呰:甯跺嵎 (TR) |
| AD5280BRUZ2002 | 鍒堕€犲晢:AD 鍒堕€犲晢鍏ㄧū:Analog Devices 鍔熻兘鎻忚堪:Single/Dual,15 V/5 V,256-Position I2C-Compatible Digital Potentiometer |
| AD5280BRUZ200-R7 | 鍔熻兘鎻忚堪:IC POT DGTL 200K 256POS 14TSSOP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 鏁�(sh霉)瀛楅浕浣嶅櫒 绯诲垪:- 妯�(bi膩o)婧�(zh菙n)鍖呰:3,000 绯诲垪:DPP 鎺ョ墖:32 闆婚樆锛堟瓙濮嗭級:10k 闆昏矾鏁�(sh霉):1 婧害绯绘暩(sh霉):妯�(bi膩o)婧�(zh菙n)鍊� 300 ppm/°C 瀛樺劜(ch菙)鍣ㄩ鍨�:闈炴槗澶� 鎺ュ彛:3 绶氫覆琛岋紙鑺墖閬告搰锛岄仦澧烇紝澧�/娓涳級 闆绘簮闆诲:2.5 V ~ 6 V 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:8-WFDFN 瑁搁湶鐒婄洡 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:8-TDFN锛�2x3锛� 鍖呰:甯跺嵎 (TR) |
| AD5280BRUZ200-R72 | 鍒堕€犲晢:AD 鍒堕€犲晢鍏ㄧū:Analog Devices 鍔熻兘鎻忚堪:Single/Dual,15 V/5 V,256-Position I2C-Compatible Digital Potentiometer |
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