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參數(shù)資料
| 型號： | AD5025BRUZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC DUAL 12BIT SPI 14TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 1 |
| 系列： | nanoDAC™ |
| 設(shè)置時間： | 5.8µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 13.5mW |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 14-TSSOP |
| 包裝： | 標準包裝 |
| 輸出數(shù)目和類型： | 2 電壓，單極；2 電壓，雙極 |
| 采樣率（每秒）： | * |
| 其它名稱： | AD5025BRUZ-REEL7DKR |
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AD5025/AD5045/AD5065
Rev. 0 | Page 17 of 28
THEORY OF OPERATION
DIGITAL-TO-ANALOG CONVERTER
The AD5025/AD5045/AD5065 are single 12-/14-/16-bit, serial
input, voltage output DACs. The parts operate from supply voltages
of 4.5 V to 5.5 V. Data is written to the AD5025/AD5045/AD5065
in a 32-bit word format via a 3-wire serial interface. The AD5025/
AD5045/AD5065 incorporate a power-on reset circuit that ensures
the DAC output powers up to a known output state. The devices
also have a software power-down mode that reduces the typical
current consumption to typically 400 nA.
Because the input coding to the DAC is straight binary, the ideal
output voltage when using an external reference is given by
N
REFIN
OUT
D
V
2
where:
D is the decimal equivalent of the binary code that is loaded to
the DAC register (0 to 65,535 for the 16-bit AD5065).
N is the DAC resolution.
DAC ARCHITECTURE
The DAC architecture of the AD5025/AD5045/AD5065 consists
of two matched DAC sections. A simplified circuit diagram is
shown in Figure 40. The four MSBs of the 16-bit data-word are
decoded to drive 15 switches, E1 to E15. Each of these switches
connects one of 15 matched resistors to either GND or a VREF
buffer output. The remaining 12 bits of the data-word drive
Switch S0 to Switch S11 of a 12-bit voltage mode R-2R ladder
network.
2R
S0
VREF
2R
S1
2R
S11
2R
E1
2R
E2
2R
E15
2R
VOUT
12-BIT R-2R LADDER
FOUR MSBs DECODED INTO
15 EQUAL SEGMENTS
0684
4-
0
06
Figure 40. DAC Ladder Structure
REFERENCE BUFFER
The AD5025/AD5045/AD5065 operate with an external reference.
Each DAC has a dedicated voltage reference pin and an on-chip
reference buffer. The reference input pin has an input range of
2.5 V to VDD. This input voltage is then used to provide a
buffered reference for the DAC core.
OUTPUT AMPLIFIER
The on-chip output buffer amplifier can generate rail-to-rail
voltages on its output, which gives an output range of 0 V to
VDD. The amplifier is capable of driving a load of 5 kΩ in
parallel with 200 pF to GND. The slew rate is 1.5 V/μs with a
to scale settling time of 13 μs.
SERIAL INTERFACE
The AD5025/AD5045/AD5065 have a 3-wire serial interface
(SYNC, SCLK, and DIN) that is compatible with SPI, QSPI, and
MICROWIRE interface standards as well as most DSPs. See
Figure 3 for a timing diagram of a typical write sequence.
INPUT REGISTER
The AD5025/AD5045/AD5065 input register is 32 bits wide
(see Figure 41). The first four bits are don’t cares. The next four
bits are the command bits, C3 to C0 (see Table 8), followed by
the 4-bit DAC address bits, A3 to A0 (see Table 7) and finally
the data bits. These data bits comprise the 12-bit, 14-bit, or 16-bit
input code, followed by eight, six, or four don’t care bits for the
AD5025/AD5045/AD5065, respectively (see Figure 41, Figure 42,
and Figure 43). These data bits are transferred to the DAC
register on the 32nd falling edge of SCLK.
Table 7. Address Commands
Address (n)
Selected DAC
Channel
A3
A2
A1
A0
0
DAC A
0
1
DAC B
0
1
Reserved
0
1
0
Reserved
1
Both DACs
Table 8. Command Definitions
Command
C3
C2
C1
C0
Description
0
Write to Input Register n1
0
1
Update DAC Register n1
0
1
0
Write to Input Register n, update all
(software LDAC)
0
1
Write to and update DAC Channel n1
0
1
0
Power down/power up DAC
0
1
0
1
Load clear code register
0
1
0
Load LDAC register
0
1
Reset (power-on reset)
1
0
Set up DCEN register (daisy-chain enable)
1
0
1
Reserved
1
Reserved
1 See Table 7.
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