
AD5025/AD5045/AD5065
Rev. 0 | Page 11 of 28
0.2
0.1
0
–0.1
–0.2
4.50
4.75
5.00
5.25
5.50
E
RRO
R
(
%
F
S
R)
VDD (V)
GAIN ERROR
FULL-SCALE ERROR
06
84
4-
03
1
Figure 18. Gain Error and Full-Scale Error vs. Supply Voltage
0.12
0.09
0.06
0.03
0
4.50
4.75
5.00
5.25
5.50
O
F
S
E
T
E
RRO
R
(
m
V
)
VDD (V)
06
84
4-
03
2
Figure 19. Offset Error Voltage vs. Supply Voltage
06
84
4-
0
64
IDD POWER UP (mA)
HI
T
S
16
14
12
10
8
6
4
2
0
1.0
1.1
1.2
1.3
1.4
1.5
Figure 20. IDD Histogram, VDD = 5.0 V
5.0
4.0
3.0
2.0
0
O
U
T
PU
T
VO
L
T
A
G
E
(
V)
TIME (s)
1.0
4.5
3.5
2.5
1.5
0.5
VDD = 5V, VREF = 4.096V
TA = 25C
1/4 SCALE TO 3/4 SCALE
3/4 SCALE TO 1/4 SCALE
OUTPUT LOADED WITH 5k
AND 200pF TO GND
02
46
8
10
12
14
06
84
4-
03
8
Figure 21. Settling Time and Typical Output Slew Rate
CH1 2V
CH3 2V
M2ms
A CH1
2.52V
3
1
T 20.4%
06
84
4-
0
39
VOUT
POR
Figure 22. Power-On Reset to 0 V
CH1 2V
CH3 2V
M2ms
A CH1
2.52V
3
1
T 20.4%
06
84
4-
0
40
Figure 23. Power-On Reset to Midscale