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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | AD2S1210BSTZ |
| 寤犲晢锛� | Analog Devices Inc |
| 鏂囦欢闋佹暩(sh霉)锛� | 7/36闋� |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | IC CONV R/D 10-16BIT 48-LQFP |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 1 |
| 椤炲瀷锛� | R/D 杞�(zhu菐n)鎻涘櫒 |
| 鍒嗚鲸鐜囷紙浣嶏級锛� | 10锛�12锛�14锛�16 b |
| 鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� | 涓茶锛屽苟鑱�(li谩n) |
| 闆诲闆绘簮锛� | 妯℃摤鍜屾暩(sh霉)瀛� |
| 闆绘簮闆诲锛� | 4.75 V ~ 5.25 V |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 48-LQFP |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 48-LQFP锛�7x7锛� |
| 鍖呰锛� | 鎵樼洡 |
| 鐢�(ch菐n)鍝佺洰閷勯爜闈細 | 790 (CN2011-ZH PDF) |
| 閰嶇敤锛� | EVAL-AD2S1210EDZ-ND - BOARD EVAL AD2S1210 |
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AD2S1210
Rev. A | Page 15 of 36
RESOLVER FORMAT SIGNALS
07
46
7-
0
23
Vr = Vp 脳 sin(蠅t)
Vb = Vs 脳 sin(蠅t) 脳 sin(胃)
(A) CLASSICAL RESOLVER
S1
S3
Va = Vs 脳 sin(蠅t) 脳 cos(胃)
S2
S4
R1
R2
胃
Vr = Vp 脳 sin(蠅t)
Vb = Vs 脳 sin(蠅t) 脳 sin(胃)
(B) VARIABLE RELUCTANCE RESOLVER
S1
S3
Va = Vs 脳 sin(蠅t) 脳 cos(胃)
S2
S4
R1
R2
胃
Figure 24. Classical Resolver vs. Variable Reluctance Resolver
A resolver is a rotating transformer, typically with a primary
winding on the rotor and two secondary windings on the stator.
In the case of a variable reluctance resolver, there are no wind-
ings on the rotor, as shown in Figure 24. The primary winding
is on the stator as well as the secondary windings, but the saliency
in the rotor design provides the sinusoidal variation in the
secondary coupling with the angular position. Either way, the
resolver output voltages (S3 S1, S2 S4) have the same
equations, as shown in Equation 1.
胃
蠅
胃
蠅
cos
sin
4
2
sin
1
3
脳
=
脳
=
t
E
S
t
E
S
0
(1)
where:
胃 is the shaft angle.
Sin蠅t is the rotor excitation frequency.
E0 is the rotor excitation amplitude.
The stator windings are displaced mechanically by 90掳 (see
Figure 24). The primary winding is excited with an ac reference.
The amplitude of subsequent coupling onto the stator secondary
windings is a function of the position of the rotor (shaft) relative to
the stator. The resolver, therefore, produces two output voltages
(S3 S1, S2 S4) modulated by the sine and cosine of shaft
angle. Resolver format signals refer to the signals derived from
the output of a resolver, as shown in Equation 1. Figure 25
illustrates the output format.
07
46
7-
0
24
0掳
S2 鈥� S4
(cos)
S3 鈥� S1
(sin)
R2 鈥� R4
(REF)
90掳
180掳
胃
270掳
360掳
Figure 25. Electrical Resolver Representation
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| V110A24M300B | CONVERTER MOD DC/DC 24V 300W |
| AD7606BSTZ-6 | IC DAS W/ADC 16BIT 6CH 64LQFP |
| AD2S1210CSTZ | IC CONV R/D VAR RES OSC 48-LQFP |
| VI-24P-MY-S | CONVERTER MOD DC/DC 13.8V 50W |
| AD7607BSTZ | IC DAS W/ADC 14BIT 8CH 64LQFP |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| AD2S1210BSTZ-DASSAULT | 鍒堕€犲晢:Analog Devices 鍔熻兘鎻忚堪: |
| AD2S1210CSTZ | 鍔熻兘鎻忚堪:IC CONV R/D VAR RES OSC 48-LQFP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - ADCs/DAC - 灏堢敤鍨� 绯诲垪:- 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 妯�(bi膩o)婧�(zh菙n)鍖呰:50 绯诲垪:- 椤炲瀷:鏁�(sh霉)鎿�(j霉)閲囬泦绯荤当(t菕ng)锛圖AS锛� 鍒嗚鲸鐜囷紙浣嶏級:16 b 閲囨ǎ鐜囷紙姣忕锛�:21.94k 鏁�(sh霉)鎿�(j霉)鎺ュ彛:MICROWIRE?锛孮SPI?锛屼覆琛�锛孲PI? 闆诲闆绘簮:妯℃摤鍜屾暩(sh霉)瀛� 闆绘簮闆诲:1.8 V ~ 3.6 V 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:40-WFQFN 瑁搁湶鐒婄洡 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:40-TQFN-EP锛�6x6锛� 鍖呰:鎵樼洡 |
| AD2S1210DSTZ | 鍔熻兘鎻忚堪:IC CONV R/D VAR RES OSC 48LQFP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - ADCs/DAC - 灏堢敤鍨� 绯诲垪:- 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 妯�(bi膩o)婧�(zh菙n)鍖呰:50 绯诲垪:- 椤炲瀷:鏁�(sh霉)鎿�(j霉)閲囬泦绯荤当(t菕ng)锛圖AS锛� 鍒嗚鲸鐜囷紙浣嶏級:16 b 閲囨ǎ鐜囷紙姣忕锛�:21.94k 鏁�(sh霉)鎿�(j霉)鎺ュ彛:MICROWIRE?锛孮SPI?锛屼覆琛岋紝SPI? 闆诲闆绘簮:妯℃摤鍜屾暩(sh霉)瀛� 闆绘簮闆诲:1.8 V ~ 3.6 V 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:40-WFQFN 瑁搁湶鐒婄洡 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:40-TQFN-EP锛�6x6锛� 鍖呰:鎵樼洡 |
| AD2S1210DSTZ | 鍒堕€犲晢:Analog Devices 鍔熻兘鎻忚堪:IC, ADC, 16BIT, PARALLEL, SERIAL, LQFP-4 |
| AD2S1210SST-EP-RL7 | 鍔熻兘鎻忚堪:妯℃暩(sh霉)杞�(zhu菐n)鎻涘櫒 - ADC IC 10-16 Bit R/D Cnvtr w/Ref Oscilltr RoHS:鍚� 鍒堕€犲晢:Analog Devices 閫氶亾鏁�(sh霉)閲�: 绲�(ji茅)妲�(g貌u): 杞�(zhu菐n)鎻涢€熺巼: 鍒嗚鲸鐜�: 杓稿叆椤炲瀷: 淇″櫔姣�: 鎺ュ彛椤炲瀷: 宸ヤ綔闆绘簮闆诲: 鏈€澶у伐浣滄韩搴�: 瀹夎棰�(f膿ng)鏍�: 灏佽 / 绠遍珨: |
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