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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | AD2S1210BSTZ |
| 寤犲晢锛� | Analog Devices Inc |
| 鏂囦欢闋佹暩(sh霉)锛� | 34/36闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC CONV R/D 10-16BIT 48-LQFP |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 1 |
| 椤炲瀷锛� | R/D 杞�(zhu菐n)鎻涘櫒 |
| 鍒嗚鲸鐜囷紙浣嶏級锛� | 10锛�12锛�14锛�16 b |
| 鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� | 涓茶锛屽苟鑱�(li谩n) |
| 闆诲闆绘簮锛� | 妯℃摤鍜屾暩(sh霉)瀛� |
| 闆绘簮闆诲锛� | 4.75 V ~ 5.25 V |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 48-LQFP |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 48-LQFP锛�7x7锛� |
| 鍖呰锛� | 鎵樼洡 |
| 鐢�(ch菐n)鍝佺洰閷勯爜闈細 | 790 (CN2011-ZH PDF) |
| 閰嶇敤锛� | EVAL-AD2S1210EDZ-ND - BOARD EVAL AD2S1210 |
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AD2S1210
Rev. A | Page 7 of 36
Parameter
Description
Limit at TMIN, TMAX
Unit
t29
Delay WR/FSYNC rising edge to SDO high-Z
15
ns min
t30
Delay from SAMPLE before WR/FSYNC falling edge
6 脳 tCK + 20 ns
ns min
t31
Delay CS falling edge to WR/FSYNC falling edge in normal mode
2
ns min
t32
A0 and A1 setup time before WR/FSYNC falling edge
2
ns min
t33
A0 and A1 hold time after WR/FSYNC falling edge2
In normal mode, A0 = 0, A1 = 0/1
24 脳 tCK + 5 ns
ns min
In configuration mode, A0 = 1, A1 = 1
8 脳 tCK + 5 ns
ns min
t34
Delay WR/FSYNC rising edge to WR/FSYNC falling edge
10
ns min
fSCLK
Frequency of SCLK input
VDRIVE = 4.5 V to 5.25 V
20
MHz
VDRIVE = 2.7 V to 3.6 V
25
MHz
VDRIVE = 2.3 V to 2.7 V
15
MHz
1 Temperature ranges are as follows: A, B grades: 鈥�40掳C to +85掳C; C, D grades: 鈥�40掳C to +125掳C.
2 A0 and A1 should remain constant for the duration of the serial readback. This may require 24 clock periods to read back the 8-bit fault information in addition to the
16 bits of position/velocity data. If the fault information is not required, A0/A1 may be released following 16 clock cycles.
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
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| VI-24P-MY-S | CONVERTER MOD DC/DC 13.8V 50W |
| AD7607BSTZ | IC DAS W/ADC 14BIT 8CH 64LQFP |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| AD2S1210BSTZ-DASSAULT | 鍒堕€犲晢:Analog Devices 鍔熻兘鎻忚堪: |
| AD2S1210CSTZ | 鍔熻兘鎻忚堪:IC CONV R/D VAR RES OSC 48-LQFP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - ADCs/DAC - 灏堢敤鍨� 绯诲垪:- 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 妯�(bi膩o)婧�(zh菙n)鍖呰:50 绯诲垪:- 椤炲瀷:鏁�(sh霉)鎿�(j霉)閲囬泦绯荤当(t菕ng)锛圖AS锛� 鍒嗚鲸鐜囷紙浣嶏級:16 b 閲囨ǎ鐜囷紙姣忕锛�:21.94k 鏁�(sh霉)鎿�(j霉)鎺ュ彛:MICROWIRE?锛孮SPI?锛屼覆琛�锛孲PI? 闆诲闆绘簮:妯℃摤鍜屾暩(sh霉)瀛� 闆绘簮闆诲:1.8 V ~ 3.6 V 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:40-WFQFN 瑁搁湶鐒婄洡 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:40-TQFN-EP锛�6x6锛� 鍖呰:鎵樼洡 |
| AD2S1210DSTZ | 鍔熻兘鎻忚堪:IC CONV R/D VAR RES OSC 48LQFP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - ADCs/DAC - 灏堢敤鍨� 绯诲垪:- 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 妯�(bi膩o)婧�(zh菙n)鍖呰:50 绯诲垪:- 椤炲瀷:鏁�(sh霉)鎿�(j霉)閲囬泦绯荤当(t菕ng)锛圖AS锛� 鍒嗚鲸鐜囷紙浣嶏級:16 b 閲囨ǎ鐜囷紙姣忕锛�:21.94k 鏁�(sh霉)鎿�(j霉)鎺ュ彛:MICROWIRE?锛孮SPI?锛屼覆琛�锛孲PI? 闆诲闆绘簮:妯℃摤鍜屾暩(sh霉)瀛� 闆绘簮闆诲:1.8 V ~ 3.6 V 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:40-WFQFN 瑁搁湶鐒婄洡 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:40-TQFN-EP锛�6x6锛� 鍖呰:鎵樼洡 |
| AD2S1210DSTZ | 鍒堕€犲晢:Analog Devices 鍔熻兘鎻忚堪:IC, ADC, 16BIT, PARALLEL, SERIAL, LQFP-4 |
| AD2S1210SST-EP-RL7 | 鍔熻兘鎻忚堪:妯℃暩(sh霉)杞�(zhu菐n)鎻涘櫒 - ADC IC 10-16 Bit R/D Cnvtr w/Ref Oscilltr RoHS:鍚� 鍒堕€犲晢:Analog Devices 閫氶亾鏁�(sh霉)閲�: 绲�(ji茅)妲�(g貌u): 杞�(zhu菐n)鎻涢€熺巼: 鍒嗚鲸鐜�: 杓稿叆椤炲瀷: 淇″櫔姣�: 鎺ュ彛椤炲瀷: 宸ヤ綔闆绘簮闆诲: 鏈€澶у伐浣滄韩搴�: 瀹夎棰�(f膿ng)鏍�: 灏佽 / 绠遍珨: |
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