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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | AD2S1210BSTZ |
| 寤犲晢锛� | Analog Devices Inc |
| 鏂囦欢闋佹暩(sh霉)锛� | 26/36闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC CONV R/D 10-16BIT 48-LQFP |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 1 |
| 椤炲瀷锛� | R/D 杞�(zhu菐n)鎻涘櫒 |
| 鍒嗚鲸鐜囷紙浣嶏級锛� | 10锛�12锛�14锛�16 b |
| 鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� | 涓茶锛屽苟鑱�(li谩n) |
| 闆诲闆绘簮锛� | 妯℃摤鍜屾暩(sh霉)瀛� |
| 闆绘簮闆诲锛� | 4.75 V ~ 5.25 V |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 48-LQFP |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 48-LQFP锛�7x7锛� |
| 鍖呰锛� | 鎵樼洡 |
| 鐢�(ch菐n)鍝佺洰閷勯爜闈細 | 790 (CN2011-ZH PDF) |
| 閰嶇敤锛� | EVAL-AD2S1210EDZ-ND - BOARD EVAL AD2S1210 |
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AD2S1210
Rev. A | Page 32 of 36
CIRCUIT DYNAMICS
LOOP RESPONSE MODEL
0
74
67
-03
7
ERROR
(ACCELERATION)
鈥�
胃IN
胃OUT
VELOCITY
k1 脳 k2
1 鈥� z鈥�1
1 鈥� bz鈥�1
1 鈥� z鈥�1
c
1 鈥� az鈥�1
c
Sin/Cos LOOKUP
Figure 38. RDC System Response Block Diagram
The RDC is a mixed-signal device that uses two ADCs to digitize
signals from the resolver and a Type II tracking loop to convert
these to digital position and velocity words.
The first gain stage consists of the ADC gain on the sine/cosine
inputs and the gain of the error signal into the first integrator.
The first integrator generates a signal proportional to velocity.
The compensation filter contains a pole and a zero that are used
to provide phase margin and reduce high frequency noise gain.
The second integrator is the same as the first and generates the
position output from the velocity signal. The sin/cos lookup has
unity gain. The values for the k1, k2, a, b, and c parameters are
outlined in Table 28.
The following equations outline the transfer functions of the
individual blocks as shown in Figure 38, which then combine to
form the complete RDC system loop response.
Integrator1 and Integrator2 transfer function
1
)
(
=
z
c
z
I
(10)
Compensation filter transfer function
1
)
(
=
bz
az
z
C
(11)
RDC open-loop transfer function
)
(
)
(
)
(
2
z
C
z
I
k2
k1
z
G
脳
=
(12)
RDC closed-loop transfer function
)
(
1
)
(
)
(
z
G
z
G
z
H
+
=
(13)
The closed-loop magnitude and phase responses are that of a
To convert G(z) into the s-plane, an inverse bilinear transforma-
tion is performed by substituting the following equation for z:
s
t
s
t
z
+
=
2
(14)
where t is the sampling period (1/4.096 MHz 鈮� 244 ns).
Substitution yields the open-loop transfer function, G(s).
)
1
(
2
)
1
(
1
)
1
(
2
)
1
(
1
4
1
)
1
(
)
(
2
b
t
s
a
t
s
t
s
st
b
a
k2
k1
s
G
+
脳
+
+
脳
+
脳
+
脳
脳
=
(15)
This transformation produces the best matching at low frequencies
(f < fSAMPLE). At such frequencies (within the closed-loop
bandwidth of the AD2S1210), the transfer function can be
simplified to
2
1
2
1
)
(
st
s
K
s
G
a
+
脳
(16)
where:
b
a
k2
k1
K
b
t
a
t
a
脳
=
+
=
+
=
)
1
(
)
1
(
2
)
1
(
)
1
(
2
)
1
(
2
1
Table 28. RDC System Response Parameters
Parameter
Description
10-bit resolution
12-bit resolution
14-bit resolution
16-bit resolution
k1 (nominal)
ADC gain
1.8/2.5
k2
Error gain
6 脳 106 脳 2
蟺
18 脳 106 脳 2
蟺
82 x 106 脳 2
蟺
66 脳 106 脳 2
蟺
a
Compensator zero coefficient
8187/8192
4095/4096
8191/8192
32,767/32,768
b
Compensator pole coefficient
509/512
4085/4096
16,359/16,384
32,757/32,768
c
Integrator gain
1/1,024,000
1/4,096,000
1/16,384,000
1/65,536,000
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| V110A24M300B | CONVERTER MOD DC/DC 24V 300W |
| AD7606BSTZ-6 | IC DAS W/ADC 16BIT 6CH 64LQFP |
| AD2S1210CSTZ | IC CONV R/D VAR RES OSC 48-LQFP |
| VI-24P-MY-S | CONVERTER MOD DC/DC 13.8V 50W |
| AD7607BSTZ | IC DAS W/ADC 14BIT 8CH 64LQFP |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| AD2S1210BSTZ-DASSAULT | 鍒堕€犲晢:Analog Devices 鍔熻兘鎻忚堪: |
| AD2S1210CSTZ | 鍔熻兘鎻忚堪:IC CONV R/D VAR RES OSC 48-LQFP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - ADCs/DAC - 灏堢敤鍨� 绯诲垪:- 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 妯�(bi膩o)婧�(zh菙n)鍖呰:50 绯诲垪:- 椤炲瀷:鏁�(sh霉)鎿�(j霉)閲囬泦绯荤当(t菕ng)锛圖AS锛� 鍒嗚鲸鐜囷紙浣嶏級:16 b 閲囨ǎ鐜囷紙姣忕锛�:21.94k 鏁�(sh霉)鎿�(j霉)鎺ュ彛:MICROWIRE?锛孮SPI?锛屼覆琛岋紝SPI? 闆诲闆绘簮:妯℃摤鍜屾暩(sh霉)瀛� 闆绘簮闆诲:1.8 V ~ 3.6 V 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:40-WFQFN 瑁搁湶鐒婄洡 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:40-TQFN-EP锛�6x6锛� 鍖呰:鎵樼洡 |
| AD2S1210DSTZ | 鍔熻兘鎻忚堪:IC CONV R/D VAR RES OSC 48LQFP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - ADCs/DAC - 灏堢敤鍨� 绯诲垪:- 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 妯�(bi膩o)婧�(zh菙n)鍖呰:50 绯诲垪:- 椤炲瀷:鏁�(sh霉)鎿�(j霉)閲囬泦绯荤当(t菕ng)锛圖AS锛� 鍒嗚鲸鐜囷紙浣嶏級:16 b 閲囨ǎ鐜囷紙姣忕锛�:21.94k 鏁�(sh霉)鎿�(j霉)鎺ュ彛:MICROWIRE?锛孮SPI?锛屼覆琛�锛孲PI? 闆诲闆绘簮:妯℃摤鍜屾暩(sh霉)瀛� 闆绘簮闆诲:1.8 V ~ 3.6 V 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:40-WFQFN 瑁搁湶鐒婄洡 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:40-TQFN-EP锛�6x6锛� 鍖呰:鎵樼洡 |
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