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參數(shù)資料
| 型號： | AD1896AYRSZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 26/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SAMP-RATEHP/CONV 24BIT 28SSOP |
| 標準包裝： | 1,500 |
| 類型： | 采樣率轉換器 |
| 應用： | 車載音頻，處理，接收器 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SSOP（0.209"，5.30mm 寬） |
| 供應商設備封裝： | 28-SSOP |
| 包裝： | 帶卷 (TR) |
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REV. A
AD1896
–7–
PIN CONFIGURATION
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AD1896
TOP VIEW
(NOT TO SCALE
)
MUTE_IN
RESET
SMODE_IN_2
SMODE_IN_1
SMODE_IN_0
BYPASS
DGND
GRPDLYS
MCLK_IN
MCLK_OUT
SDATA_I
VDD_IO
LRCLK_I
SCLK_I
MUTE_OUT
WLNGTH_OUT_1
WLNGTH_OUT_0
SMODE_OUT_1
SMODE_OUT_0
TDM_IN
DGND
MMODE_2
MMODE_1
MMODE_0
SCLK_O
VDD_CORE
SDATA_O
LRCLK_O
PIN FUNCTION DESCRIPTIONS
Pin No.
IN/OUT
Mnemonic
Description
1IN
GRPDLYS
Group Delay High = Short, Low = Long
2IN
MCLK_IN
Master Clock or Crystal Input
3
OUT
MCLK_OUT
Master Clock Output or Crystal Output
4IN
SDATA_I
Input Serial Data (at Input Sample Rate)
5
IN/OUT
SCLK_I
Master/Slave Input Serial Bit Clock
6
IN/OUT
LRCLK_I
Master/Slave Input Left/Right Clock
7IN
VDD_IO
3.3 V/5 V Input/Output Digital Supply Pin
8IN
DGND
Digital Ground Pin
9IN
BYPASS
ASRC Bypass Mode, Active High
10
IN
SMODE_IN_0
Input Port Serial Interface Mode Select Pin 0
11
IN
SMODE_IN_1
Input Port Serial Interface Mode Select Pin 1
12
IN
SMODE_IN_2
Input Port Serial Interface Mode Select Pin 2
13
IN
RESET
Reset Pin, Active Low
14
IN
MUTE_IN
Mute Input Pin—Active High Normally Connected to MUTE_OUT
15
OUT
MUTE_OUT
Output Mute Control, Active High
16
IN
WLNGTH_OUT_1
Hardware Selectable Output Wordlength—Select Pin 1
17
IN
WLNGTH_OUT_0
Hardware Selectable Output Wordlength—Select Pin 0
18
IN
SMODE_OUT_1
Output Port Serial Interface Mode Select Pin 1
19
IN
SMODE_OUT_0
Output Port Serial Interface Mode Select Pin 0
20
IN
TDM_IN
Serial Data Input
* (Only for Daisy-Chain Mode). Ground when not used.
21
IN
DGND
Digital Ground Pin
22
IN
VDD_CORE
3.3 V Digital Supply Pin
23
OUT
SDATA_O
Output Serial Data (at Output Sample Rate)
24
IN/OUT
LRCLK_O
Master/Slave Output Left/Right Clock
25
IN/OUT
SCLK_O
Master/Slave Output Serial Bit Clock
26
IN
MMODE_0
Master/Slave Clock Ratio Mode Select Pin 0
27
IN
MMODE_1
Master/Slave Clock Ratio Mode Select Pin 1
28
IN
MMODE_2
Master/Slave Clock Ratio Mode Select Pin 2
*Also used to input matched-phase mode data.
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