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參數(shù)資料
| 型號(hào)： | AD1896AYRSZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SAMP-RATEHP/CONV 24BIT 28SSOP |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 類型： | 采樣率轉(zhuǎn)換器 |
| 應(yīng)用： | 車載音頻，處理，接收器 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SSOP |
| 包裝： | 帶卷 (TR) |
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REV. A
AD1896
–23–
TDM MODE APPLICATION
In TDM mode, several AD1896s can be daisy-chained together
and connected to the serial input port of a SHARC DSP. The
AD1896 contains a 64-bit parallel load shift register. When the
LRCLK_O pulse arrives, each AD1896 parallel loads its left and
right data into the 64-bit shift register. The input to the shift
register is connected to TDM_IN, while the output is connected
to SDATA_O. By connecting the SDATA_O to the TDM_IN
of the next AD1896, a large shift register is created, which is
clocked by SCLK_O.
The number of AD1896s that can be daisy-chained together is
limited by the maximum frequency of SCLK_O, which is about
25 MHz. For example, if the output sample rate, fS, is 48 kHz,
up to eight AD1896s could be connected since 512
fS is less
than 25 MHz. In master/TDM mode, the number of AD1896s
that can be daisy-chained is fixed to four.
MSB
1/fs
TDM MODE – 16 BITS TO 24 BITS PER CHANNEL
LEFT CHANNEL
RIGHT CHANNEL
LEFT CHANNEL
RIGHT CHANNEL
MSB
LSB
MSB
LSB
MSB
LSB
LRCLK
SCLK
SDATA
LRCLK
SCLK
SDATA
LRCLK
SCLK
SDATA
LRCLK
SCLK
SDATA
NOTES
1 LRCLK NORMALLY OPERATES AT ASSOCIATIVE INPUT OR OUTPUT SAMPLE FREQUENCY (f
s).
2 SCLK FREQUENCY IS NORMALLY 64
LRCLK EXCEPT FOR TDM MODE WHICH IS N
64
fs,
WHERE N = NUMBER OF STEREO CHANNELS IN THE TDM CHAIN, IN MASTER MODE N = 4.
3 PLEASE NOTE THAT 8 BITS OF EACH 32-BIT SUBFRAME ARE USED FOR TRANSMITTING
MATCHED-PHASE MODE DATA. PLEASE REFER TO FIGURE 14.
MSB
I2S MODE – 16 BITS TO 24 BITS PER CHANNEL
RIGHT-JUSTIFIED MODE – SELECT NUMBER OF BITS PER CHANNEL
LEFT-JUSTIFIED MODE – 16 BITS TO 24 BITS PER CHANNEL
Figure 10. Input/Output Serial Data Formats
AD1896
TDM_IN
SDATA_O
LRCLK_O
PHASE-MASTER
M1
M2
M0
0
SCLK_O
SHARC
DSP
DR0
RFS0
RCLK0
SLAVE-1
SLAVE-n
STANDARD MODE
MATCHED-PHASE MODE
AD1896
TDM_IN
SDATA_O
LRCLK_O
M1
M2
M0
0
1
0
SCLK_O
AD1896
TDM_IN
SDATA_O
LRCLK_O
M1
M2
M0
SCLK_O
0
1
0
SCLK
LRCLK
Figure 11. Daisy-Chain Configuration for TDM Mode (All AD1896s Being Clock-Slaves)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD1896YRS | 制造商:Analog Devices 功能描述: 制造商:Rochester Electronics LLC 功能描述:192KHZ 8:1 STEREO ASYNC SAMPLE RATE CONV - Bulk |
| AD1896YRSRL | 制造商:Analog Devices 功能描述: |
| AD1898 | 制造商:Analog Devices 功能描述:- Bulk |
| AD-18B | 制造商:Altas 功能描述: |
| AD18T | 制造商:Opto 22 功能描述:I/O Module; 5 VDC @ 170 mA; 0 to degC; UL, CSA, CE Certified 制造商:Opto 22 功能描述:I/O MODULE 制造商:Opto 22 功能描述:I/O MODULE; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; No. of Analog Inputs:1; No. of Outputs:1; Resolution:12 Bits; Signal Input Type:Thermocouple ;RoHS Compliant: No |
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