參數(shù)資料
型號(hào)： AD1896AYRSZRL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 15/28頁(yè)
文件大?。?/td> 0K
描述： IC SAMP-RATEHP/CONV 24BIT 28SSOP
標(biāo)準(zhǔn)包裝： 1,500
類(lèi)型： 采樣率轉(zhuǎn)換器
應(yīng)用： 車(chē)載音頻，處理，接收器
安裝類(lèi)型： 表面貼裝
封裝/外殼： 28-SSOP（0.209"，5.30mm 寬）
供應(yīng)商設(shè)備封裝： 28-SSOP
包裝： 帶卷 (TR)
REV. A
AD1896
–22–
AD1896
MCLK_I
MCLK_O
C1
C2
R
Figure 9a. Fundamental-Mode Circuit Configuration
AD1896
MCLK_I
MCLK_O
C1
C2
R
1nF
L1
Figure 9b. Third-Overtone Circuit Configuration
There are, of course, maximum and minimum operating fre-
quencies for the AD1896 master clock. The maximum master
clock frequency at which the AD1896 is guaranteed to operate is
30 MHz. A frequency of 30 MHz is more than sufficient to
sample rate convert sampling frequencies of 192 kHz + 12%.
The minimum required frequency for the master clock generation
for the AD1896 depends upon the input and output sample
rates. The master clock has to be at least 138 times greater than
the maximum input or output sample rate.
Serial Data Ports—Data Format
The serial data input port mode is set by the logic levels on the
SMODE_IN_0/SMODE_IN_1/SMODE_IN_2 pins. The serial
data input port modes available are left justified, I
2S, and right
justified (RJ), 16, 18, 20, or 24 bits as defined in Table I.
Table I. Serial Data Input Port Mode
SMODE_IN_[0:2]
Interface Format
21
0
00
0
Left Justified
00
1
I
2S
01
0Undefined
01
1Undefined
10
0Right Justified, 16 Bits
10
1Right Justified, 18 Bits
11
0Right Justified, 20 Bits
11
1Right Justified, 24 Bits
The serial data output port mode is set by the logic levels on the
SMODE_OUT_0/SMODE_OUT_1 and WLNGTH_OUT_0/
WLNGTH_OUT_1 pins. The serial mode can be changed to
left justified, I
2S, right justified, or TDM as defined in the fol-
lowing table. The output word width can be set by using the
WLNGTH_OUT_0/WLNGTH_OUT_1 pins as shown in
Table III. When the output word width is less than 24 bits, dither
is added to the truncated bits. The right justified serial data out
mode assumes 64 SCLK_O cycles per frame, divided evenly for
left and right. Please note that 8 bits of each 32-bit subframe are
used for transmitting matched-phase mode data. Please refer to
Figure 14. The AD1896 also supports 16-bit, 32-clock packed
input and output serial data in LJ and I
2S format.
Table II. Serial Data Output Port Mode
SMODE_OUT_[0:1]
Interface Format
10
00
Left Justified (LJ)
01
I
2S
10
TDM Mode
11
Right Justified (RJ)
Table III. Word Width
WLNGTH_OUT_[0:1]
Word Width
10
00
24 Bits
01
20 Bits
10
18 Bits
11
16 Bits
The following timing diagrams show the serial mode formats.
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