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參數(shù)資料
| 型號： | AD1896AYRSZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 18/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CONV SAMPLE RATE ASYNC 28SSOP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 采樣率轉(zhuǎn)換器 |
| 應(yīng)用： | 車載音頻，處理，接收器 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SSOP |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 776 (CN2011-ZH PDF) |
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REV. A
AD1896
–25–
Matched-Phase Mode
The matched-phase mode is the mode discussed in the Theory of
Operation section that eliminates the phase mismatch between
multiple AD1896s. The master AD1896 device transmits
its fS_OUT/fS_IN ratio through the SDATA_O pin to the slave
AD1896’s TDM_IN pins. The slave AD1896s receive the
transmitted fS_OUT/fS_IN ratio and use the transmitted fS_OUT/
fS_IN ratio instead of their own internally derived fS_OUT/fS_IN
ratio. The master device can have both its serial ports in slave
mode as depicted or either one in master mode. The slave
AD1896s must have their MMODE_2, MMODE_1, and
MMODE_0 pins set to 100, respectively. LRCLK_I and
LRCLK_O may be asynchronous with respect to each other in
this mode. Another requirement of the matched-phase mode is
that there must be 32 SCLK_O cycles per subframe. The
AD1896 will support the matched-phase mode for all serial
output data formats, left justified, I
2S, right justified, and
TDM. In the case of TDM, the AD1896 shown in the TDM
mode operation figure with its TDM_IN tied to ground would be
configured as the master, while the rest of the AD1896s in the
chain would be configured as slaves with their MMODE_2,
MMODE_1, and MMODE_0 pins set to 100, respectively.
Please note that in the left-justified, I
2S, and TDM modes,
the lower eight bits of each channel subframe are used to
transmit the matched-phase data. In right-justified mode, the
upper eight bits are used to transmit the matched-phase data.
This is shown in Figures 14a and 14b.
Bypass Mode
When the BYPASS pin is asserted high, the input data bypasses
the sample rate converter and is sent directly to the serial output
port. Dithering of the output data when the word length is set
to less than 24 bits is disabled. This mode is ideal when the
input and output sample rates are the same and LRCLK_I and
LRCLK_O are synchronous with respect to each other. This
mode can also be used for passing through non-AUDIO data
since no processing is performed on the input data in this mode.
AUDIO DATA LEFT CHANNEL, 24 BITS
MATCHED-PHASE
DATA, 8 BITS
AUDIO DATA RIGHT CHANNEL, 24 BITS
MATCHED-PHASE
DATA, 8 BITS
Figure 14a. Matched-Phase Data Transmission (Left-Justified, I2S, and TDM Mode)
AUDIO DATA LEFT CHANNEL,
16 BITS – 24 BITS
AUDIO DATA RIGHT CHANNEL,
16 BITS – 24 BITS
MATCHED-PHASE
DATA, 8 BITS
MATCHED-PHASE
DATA, 8 BITS
Figure 14b. Matched-Phase Data Transmission (Right-Justified Mode)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD1896AYRSZ | 制造商:Analog Devices 功能描述:IC, SAMPLE RATE CONVERTER, SSOP-28 |
| AD1896AYRSZRL | 功能描述:IC SAMP-RATEHP/CONV 24BIT 28SSOP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:- 其它有關(guān)文件:STA321 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6 |
| AD1896YRS | 制造商:Analog Devices 功能描述: 制造商:Rochester Electronics LLC 功能描述:192KHZ 8:1 STEREO ASYNC SAMPLE RATE CONV - Bulk |
| AD1896YRSRL | 制造商:Analog Devices 功能描述: |
| AD1898 | 制造商:Analog Devices 功能描述:- Bulk |
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