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參數(shù)資料
| 型號： | AD1896AYRSZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 17/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CONV SAMPLE RATE ASYNC 28SSOP |
| 標準包裝： | 1 |
| 類型： | 采樣率轉(zhuǎn)換器 |
| 應(yīng)用： | 車載音頻，處理，接收器 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SSOP |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 776 (CN2011-ZH PDF) |
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REV. A
AD1896
–24–
Serial Data Port Master Clock Modes
Either of the AD1896 serial ports can be configured as a master
serial data port. However, only one serial port can be a master
while the other has to be a slave. In master mode, the AD1896
requires a 256
fS, 512 fS, or 768 fS master clock (MCLK_I).
For a maximum master clock frequency of 30 MHz, the maxi-
mum sample rate is limited to 96 kHz. In slave mode, sample
rates up to 192 kHz can be handled.
When either of the serial ports is operated in master mode, the
master clock is divided down to derive the associated left/
right subframe clock (LRCLK) and serial bit clock (SCLK).
The master clock frequency can be selected for 256, 512, or 768
times the input or output sample rate. Both the input and out-
put serial ports will support master mode LRCLK and SCLK
generation for all serial modes, left justified, I
2S, right justified, and
TDM for the output serial port.
Table IV. Serial Data Port Clock Modes
MMODE_0/
MMODE_1/
MMODE_2
Interface Format
210
000Both serial ports are in slave mode.
001
Output serial port is master with 768
fS_OUT.
010Output serial port is master with 512
fS_OUT.
011
Output serial port is master with 256
fS_OUT.
100Matched-phase Mode
101
Input serial port is master with 768
fS_IN.
110
Input serial port is master with 512
fS_IN.
111
Input serial port is master with 256
fS_IN.
AD1896
TDM_IN
SDATA_O
LRCLK_O
CLOCK-MASTER
AND
PHASE-MASTER
M1
M2
M0
1
0
1
SCLK_O
SHARC
DSP
DR0
RFS0
RCLK0
SLAVE-1
SLAVE-n
STANDARD MODE
MATCHED-PHASE MODE
AD1896
TDM_IN
SDATA_O
LRCLK_O
M1
M2
M0
0
1
0
SCLK_O
AD1896
TDM_IN
SDATA_O
LRCLK_O
M1
M2
M0
SCLK_O
0
1
0
Figure 12. Daisy-Chain Configuration for TDM Mode (First AD1896 Being Clock-Master)
MATCHED-PHASE MODE (NON-TDM MODE) APPLICATION
AD1896
SLAVE1
M2 M1 M0
AD1896
TDM_IN
SDATA_I
LRCLK_I
SCLK_I
MCLK
RESET
SDATA_O
LRCLK_O
SCLK_O
PHASE-MASTER
M2 M1 M0
AD1896
SLAVE2
M2 M1 M0
AD1896
SLAVEn
M2 M1 M0
0
1
0
1
0
1
0
LRCLKI (fS_IN)
SCLKI
LRCLKO (fS_OUT)
SCLKO (64fS_OUT)
MCLK
RESET
SDOm
SDO1
SDO2
SDOn
TDM_IN
SDATA_I
LRCLK_I
SCLK_I
MCLK
RESET
SDATA_O
LRCLK_O
SCLK_O
TDM_IN
SDATA_I
LRCLK_I
SCLK_I
MCLK
RESET
SDATA_O
LRCLK_O
SCLK_O
TDM_IN
SDATA_I
LRCLK_I
SCLK_I
MCLK
RESET
SDATA_O
LRCLK_O
SCLK_O
Figure 13. Typical Configuration for Matched-Phase Mode Operation
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD1896AYRSZ | 制造商:Analog Devices 功能描述:IC, SAMPLE RATE CONVERTER, SSOP-28 |
| AD1896AYRSZRL | 功能描述:IC SAMP-RATEHP/CONV 24BIT 28SSOP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:- 其它有關(guān)文件:STA321 View All Specifications 標準包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6 |
| AD1896YRS | 制造商:Analog Devices 功能描述: 制造商:Rochester Electronics LLC 功能描述:192KHZ 8:1 STEREO ASYNC SAMPLE RATE CONV - Bulk |
| AD1896YRSRL | 制造商:Analog Devices 功能描述: |
| AD1898 | 制造商:Analog Devices 功能描述:- Bulk |
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