參數(shù)資料
型號(hào)： AD1893
廠商： Analog Devices, Inc.
英文描述： Low Cost SamplePort 16-Bit Stereo Asynchronous Sample Rate Converter(低成本采樣端口16位立體聲異步采樣率轉(zhuǎn)換器)
中文描述： 低成本SamplePort 16位立體聲異步采樣率轉(zhuǎn)換器（低成本采樣端口16位立體聲異步采樣率轉(zhuǎn)換器）
文件頁(yè)數(shù)： 14/20頁(yè)
文件大?。?/td> 338K
代理商： AD1893
AD1893
–14–
REV. 0
Some applications using multiple AD1893s may desire to use
the same master clock frequency for all the SamplePorts,
supplied by a single crystal. The crystal output can be buffered
with a 74HCXX gate and distributed to the other XTAL_I
inputs, as shown in Figure 10.
Figure 10. Buffered 16 MHz Crystal Connection
Power-Down Mode
The AD1893 includes a power-down control input pin
PWRDWN. This control signal is active HI, and puts the
AD1893 in an inactive state with very low power dissipation.
The PWRDWN pin should be connected LO when normal
operation of the AD1893 is desired.
Control Signals
The SETLSLW, BKPOL_I, BKPOL_O, MODE0_I, MODE1_I,
MODE0_O and MODE1_O inputs are asynchronous signals in
that they need obey no particular timing relation to the crystal
frequency or the sample clocks. Ordinarily, these pins are
hardwired or connected to an I/O register for microprocessor
control. The only timing requirement on these pins is that the
control signals are stable and valid before the first serial input
data bit (i.e., the MSB) is presented to the AD1893.
Reset
Figure 27 shows the reset timing for the AD1893 SamplePort. A
crystal (or resonator) must be connected to the AD1893 when
RESET
is asserted, and the bit clocks, the word clocks and the
left/
right
clocks may also be running. When the AD1893 comes
out of reset, it defaults to a F
SIN
to F
SOUT
ratio of 1:1. The filter
pipeline is not cleared. However, the mute output goes HI for at
least 128 cycles, adequate to allow the pipeline to clear. If F
SIN
differs significantly from F
SOUT
, then the AD1893 sample clock
servo control loop also has to settle. While settling, the mute
output will be HI. After the external system resets the AD1893,
it should wait until the mute output goes LO before clocking in
serial data.
There is no requirement for using the
RESET
pin at power-up
or when the input or output sample rate changes. If it is not
used, the AD1893 will settle to the sample clocks supplied
within
≈
200 ms in fast-settling mode or within
≈
800 ms in
slow-settling mode.
APPLICATION ISSUES
Dither
Due to the large output word length, no redithering of the
AD1893 output is necessary. This assumes that the input is
properly dithered and the user retains the same or greater
number of output bits as there are input bits. The AD1893
output bit stream may thus be used directly as the input to
downstream digital audio processors, storage media or output
devices.
If the AD1893 is to be used to dramatically downsample (i.e.,
output sample frequency is much lower than input sample
frequency), the input should be sufficiently dithered to account
for the limiting of the input signal bandwidth (which reduces the
RMS level of the input dither). No dither is internally used or
applied to the audio data in the AD1893 SamplePort.
Decoupling and PCB Layout
The AD1893 ASRC has two power and two ground connections
to minimize output switching noise and ground bounce. [Pins
14 (DIP) and 16 (TQFP) are actually control inputs, and
should be tied LO, but need not be decoupled.] The DIP
version places the power and ground pins at the center of the
device to optimize switching performance. The AD1893 should
be decoupled with two high quality 0.1
μ
F or 0.01
μ
F ceramic
capacitors (preferably surface mount chip capacitors, due to
their low inductance), one between each V
DD
/GND pair. Best
practice PCB layout and interconnect guidelines should be
followed. This may include terminating the bit clocks or the left/
right
clocks if excessive overshoot or undershoot is evident and
avoiding parallel PCB traces to minimize digital crosstalk
between clocks and control lines. Note that DIP and TQFP
sockets reduce electrical performance due to the additional
inductance they impose; sockets should therefore be used only
when required.
Master Clock
Using a 16 MHz crystal, the nominal range of sample frequencies
that the AD1893 accepts is from 8 kHz to 56 kHz. Other
sample frequency ranges are possible by linearly scaling the
crystal frequency. For example, a 12 MHz crystal would yield a
sample frequency range of 6 kHz to 42 kHz. The approximate
relative upper bound sample frequency is the crystal frequency
divided by 286; the approximate relative lower bound sample
frequency is the crystal frequency divided by 2000. The audio
performance will not degrade if the sample frequencies are kept
within these bounds. The AD1893 SamplePort is production
tested at 16 MHz. Note that due to finite register length con-
straints, there is a minimum input sample frequency (L
R
_I).
The allowable input and output sample frequency ranges for
crystal frequencies of 16 MHz and 12 MHz are shown in
Figures 11 and 12.
Figure 11. Allowable Input and Output Sample Frequencies
F
crystal
= 16 MHz Case
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD1893JN 制造商:Analog Devices 功能描述:Sample Rate Converter 28-Pin PDIP W 制造商:Rochester Electronics LLC 功能描述:LOW COST ASRC PDIP 28-PIN - Bulk
AD1893JNZ 制造商:Analog Devices 功能描述:Sample Rate Converter 28-Pin PDIP W
AD1893JST 制造商:Analog Devices 功能描述:Sample Rate Converter 44-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:LOW COST ASRC 44-PIN TQFP - Tape and Reel 制造商:Analog Devices 功能描述:IC ASR CONVERTER 16 BIT
AD1893JSTZ 功能描述:IC SAMPLE-RATE CONV 16BIT 44TQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 線性 - 音頻處理 系列:SamplePort™ 其它有關(guān)文件:STA321 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:Sound Terminal™ 類(lèi)型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類(lèi)型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱(chēng):497-11050-6
AD1893JSTZRL 功能描述:IC SAMPLE-RATE CONV 16BIT 44TQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 線性 - 音頻處理 系列:SamplePort™ 其它有關(guān)文件:STA321 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:Sound Terminal™ 類(lèi)型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類(lèi)型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱(chēng):497-11050-6
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