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參數(shù)資料
| 型號(hào)： | AD10242BZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 3/16頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC DUAL 12BIT 68-CLCC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 40M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 2W |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 68-CLCC |
| 供應(yīng)商設(shè)備封裝： | 68-CLCC（24.13x24.13） |
| 包裝： | 托盤(pán) |
| 輸入數(shù)目和類(lèi)型： | 6 個(gè)單端，雙極 |
| 配用： | AD10242/PCB-ND - KIT EVAL PCB FOR AD10242 |
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AD10242
–11–
REV. C
If a logic threshold other than the nominal 1.6 V is required,
the following equations show how to use an external resistor,
Rx, to raise or lower the trip point (see Figure 4, R1 = 17 k
,
R2 = 8 k
).
V
RRx
RR
RRx
R Rx
1
52
12
1
2
=
++
to lower logic threshold.
0.01 F
ENCODE
SOURCE
ENCODE
AD10242
Rx
Vl
5V
R1
R2
Figure 7. Lower Threshold for Encode
V
R
RRx
1
52
2
1
=
+
to raise logic threshold.
0.01 F
ENCODE
SOURCE
ENCODE
AD10242
Rx
Vl
5V
R1
R2
AVCC
Figure 8. Raise Logic Threshold for Encode
While the single-ended encode will work well for many applica-
tions, driving the encode differentially will provide increased
performance. Depending on circuit layout and system noise, a
1 dB to 3 dB improvement in SNR can be realized. It is recom-
mended that the encode signal be ac-coupled into the ENCODE
and
ENCODE pins.
The simplest option is shown below. The low jitter TTL signal
is coupled with a limiting resistor, typically 100
, to the primary
side of an RF transformer (these transformers are inexpensive
and readily available; part number in Figures 9 and 10 is from
Mini-Circuits). The secondary side is connected to the ENCODE
and
ENCODE pins of the converter. Since both encode inputs
are self-biased, no additional components are required.
TTL
ENCODE
AD10242
100
T1–1T
Figure 9. TTL Source—Differential Encode
If no TTL source is available, a clean sine wave may be substi-
tuted. In the case of the sine source, the matching network is
shown below. Since the matching transformer specified is a 1:1
impedance ratio, the load resistor R should be selected to match
the source impedance. The input impedance of the AD9042
is negligible in most cases.
ENCODE
AD10242
R
T1–1T
SINE
SOURCE
Figure 10. Sine Source—Differential Encode
If a low jitter ECL clock is available, another option is to ac-couple
a differential ECL signal to the encode input pins, as shown
in Figure 11. The capacitors shown here should be chip capaci-
tors but do not need to be of the low inductance variety.
ENCODE
AD10242
ECL
GATE
0.1 F
–VS
510
Figure 11. Differential ECL for Encode
As a final alternative, the ECL gate may be replaced by an ECL
comparator. The input to the comparator could then be a logic
signal or a sine signal.
ENCODE
AD10242
0.1 F
–VS
50
AD96687 (1/2)
510
Figure 12. ECL Comparator for Encode
Care should be taken not to overdrive the encode input pin when
ac-coupled. Although the input circuitry is electrically protected
from overvoltage or undervoltage conditions, improper circuit
operations may result from overdriving the encode input pin.
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