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參數(shù)資料
| 型號： | ACS8944T |
| 廠商： | Semtech |
| 文件頁數(shù)： | 1/24頁 |
| 文件大小： | 0K |
| 描述： | IC JITTER ATT MULT PLL 48-QFN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時鐘/頻率發(fā)生器，多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | SONET/SDH |
| 輸入： | LVPECL |
| 輸出： | LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 155.52MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 48-QFN（7x7） |
| 包裝： | 管件 |
Revision 3/November 2006 Semtech Corp.
Page 1
www.semtech.com
ACS8944 JAM PLL
ADVANCED COMMUNICATIONS
FINAL
Jitter Attenuating, Multiplying Phase Locked Loop
for OC-12/STM-4
ADVANCED COMMUNICATIONS
FINAL
DATASHEET
The ACS8944 JAM PLL is a Jitter- Attenuating, Multiplying
Phase-Locked Loop, for generating low jitter output clocks
compliant up to SONET OC-12 and STM-4 622.08 MHz
specifications. Its primary function is to clean up clock
jitter for high performance optical line cards which have
OC-3 or OC-12 SONET serializers or framers, and is the
entry level device in Semtech’s range of JAM PLLs.
The ACS8944 JAM PLL has a single differential LVPECL
input and a single differential LVPECL output. Both input
and output clock frequencies are individually
programmable and can be hardware configured to be any
of 19.44 MHz, 38.88 MHz, 77.76 MHz or 155.52 MHz.
The headline jitter figures quoted for the ACS8944
depend on the frequency band over which the jitter is
measured. For example, typical stand-alone output jitter
is typically 2.8 ps rms (well within GR-253-CORE[8]
specification requirements of 16.1 ps rms for OC-12 and
64.3 ps rms for OC-3).
The device's operating bandwidth (and consequently the
jitter attenuation point relating to this bandwidth) is set by
external passive components in a differential
arrangement which offers good noise immunity.
Meets rms jitter requirements of:
Telcordia GR-253-CORE[8] for OC-3 and OC-12
ITU-T G.813[4]/G.812[3] for STM-1 and STM-4 rates
rates
Typical jitter generation down to:
0.3 ps rms for 250 kHz to 5 MHz band for G.813,
or EN300-462, at STM-4 (OC-12) rates
2.8 ps rms for 12 kHz to 20 MHz band (against
4.02 ps rms for GR-253-CORE at OC-48 rate)
Pull-in range ±400 ppm about center input frequency
Frequency translation e.g. 19.44 MHz to 155.52 MHz
3.3 V operation, - 40 to +85°C temperature range
Small outline leadless 7 mm x 7 mm QFN48 package
Demonstration Board available on request
PLL bandwidth and jitter peaking are fully adjustable.
Supports bandwidths from 2 kHz for superior input
jitter filtering
Lead (Pb)-free version available (ACS8944T), RoHS[9]
and WEEE[10] compliant
Note...For items marked [1],[2], etc. references are given in full
in the Reference Section on page 21.
Figure 1 Simplified Block Diagram of the ACS8944 JAM PLL
Block Diagram
Introduction
Features
Loop
Filter
PFD
Charge
Pump
2.5 GHz
VCO
Frequency
Divider
Control and Monitor
Differential
Clock Output
LVPECL
155.52 MHz
77.76 MHz
38.88 MHz
19.44 MHz
LO
C
K
B
Differential
Input Reference
LVPECL
155.52 MHz
77.76 MHz
38.88 MHz
19.44 MHz
RESETB
CFG_OUT0
CFG_OUT1
CFG_OUT2
CFG_OUT3
OP_FSEL
VC
EXT1
EXT2
F8944D_001Blockdiag_02
LVPECL
Frequency
Divider
EXT3
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| ACS8946T | 功能描述:IC JITTER ATT MULT PLL 48-QFN RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| ACS8947T | 功能描述:IC JITTER ATT MULT PLL 48-QFN RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| ACS9010 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Optoelectronic |
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