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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | A10V10B-VQG80C |
| 寤犲晢锛� | Microsemi SoC |
| 鏂囦欢闋佹暩(sh霉)锛� | 9/98闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC FPGA 1200 GATES 80-VQFP COM |
| 妯欐簴鍖呰锛� | 90 |
| 绯诲垪锛� | ACT™ 1 |
| LAB/CLB鏁�(sh霉)锛� | 295 |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 57 |
| 闁€鏁�(sh霉)锛� | 1200 |
| 闆绘簮闆诲锛� | 2.7 V ~ 3.6 V |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 宸ヤ綔婧害锛� | 0°C ~ 70°C |
| 灏佽/澶栨锛� | 80-TQFP |
| 渚涙噳鍟嗚ō鍌欏皝瑁濓細 | 80-VQFP锛�14x14锛� |
绗�1闋�绗�2闋�绗�3闋�绗�4闋�绗�5闋�绗�6闋�绗�7闋�绗�8闋�鐣跺墠绗�9闋�绗�10闋�绗�11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�绗�18闋�绗�19闋�绗�20闋�绗�21闋�绗�22闋�绗�23闋�绗�24闋�绗�25闋�绗�26闋�绗�27闋�绗�28闋�绗�29闋�绗�30闋�绗�31闋�绗�32闋�绗�33闋�绗�34闋�绗�35闋�绗�36闋�绗�37闋�绗�38闋�绗�39闋�绗�40闋�绗�41闋�绗�42闋�绗�43闋�绗�44闋�绗�45闋�绗�46闋�绗�47闋�绗�48闋�绗�49闋�绗�50闋�绗�51闋�绗�52闋�绗�53闋�绗�54闋�绗�55闋�绗�56闋�绗�57闋�绗�58闋�绗�59闋�绗�60闋�绗�61闋�绗�62闋�绗�63闋�绗�64闋�绗�65闋�绗�66闋�绗�67闋�绗�68闋�绗�69闋�绗�70闋�绗�71闋�绗�72闋�绗�73闋�绗�74闋�绗�75闋�绗�76闋�绗�77闋�绗�78闋�绗�79闋�绗�80闋�绗�81闋�绗�82闋�绗�83闋�绗�84闋�绗�85闋�绗�86闋�绗�87闋�绗�88闋�绗�89闋�绗�90闋�绗�91闋�绗�92闋�绗�93闋�绗�94闋�绗�95闋�绗�96闋�绗�97闋�绗�98闋�
17
Hi R e l F P GA s
1 200 XL T i m i ng Mo de l *
*Values shown for A1280XL鈥�1 at worst-case military conditions.
Input module predicted routing delay.
Output Delays
Internal Delays
Input Delays
tINH = 0.0 ns
tINSU = 0.4 ns
I/O Module
D
Q
tINGL = 3.7 ns
tINYL = 1.7 ns t
IRD2 = 5.2 ns
Combinatorial
Logic Module
tPD = 3.7 ns
Sequential
Logic Module
I/O Module
tRD1 = 1.7 ns
tDLH = 6.6 ns
I/O Module
ARRAY
CLOCKS
FMAX = 110 MHz
Combin-
atorial
Logic
included
in tSUD
D
Q
D
Q
tOUTH = 0.0 ns
tOUTSU = 0.4 ns
tGLH = 5.9 ns
tDLH = 6.6 ns
tENHZ = 7.5 ns
tRD1 = 1.7 ns
tCO = 3.7 ns
tSU = 0.4 ns
tHD = 0.0 ns
tRD4 = 3.7 ns
tRD8 = 7.0 ns
Predicted
Routing
Delays
tCKH = 7.1 ns
G
FO = 256
tRD2 = 2.5 ns
tLCO = 10.7 ns (64 loads, pad-pad)
鐩搁棞PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| A1010B-1VQ80C | IC FPGA 1200 GATES 80-VQFP COM |
| A1010B-1VQG80C | IC FPGA 1200 GATES 80-VQFP COM |
| 5745175-1 | CONN BACKSHELL DB50 DIE CAST |
| 5745172-1 | CONN BACKSHELL DB15 DIE CAST |
| A1010B-2PQG100C | IC FPGA 1200 GATES 100-PQFP COM |
鐩搁棞浠ｇ悊鍟�/鎶€琛撳弮鏁�(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| A10V20 | 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:5V and 3.3V Families fully compatible with JEDEC specifications |
| A10V20B | 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:ACT 1 Series FPGAs |
| A10V20B-1CQ84B | 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:ACT 1 Series FPGAs |
| A10V20B-1CQ84C | 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:ACT 1 Series FPGAs |
| A10V20B-1CQ84I | 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:ACT 1 Series FPGAs |
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