A1 28 0A T i m i n g C har a c t e r i st i c s (continued) (W or" />
參數(shù)資料
型號(hào)： A10V10B-VQG80C
廠商： Microsemi SoC
文件頁(yè)數(shù)： 25/98頁(yè)
文件大?。?/td> 0K
描述： IC FPGA 1200 GATES 80-VQFP COM
標(biāo)準(zhǔn)包裝： 90
系列： ACT™ 1
LAB/CLB數(shù)： 295
輸入/輸出數(shù)： 57
門數(shù)： 1200
電源電壓： 2.7 V ~ 3.6 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 70°C
封裝/外殼： 80-TQFP
供應(yīng)商設(shè)備封裝： 80-VQFP（14x14）
31
Hi R e l F P GA s
A1 28 0A T i m i n g C har a c t e r i st i c s (continued)
(W or s t - C as e M i l i t a r y Cond i t i o n s , V CC = 4.5 V, TJ = 1 25°C)
‘–1’ Speed
‘Std’ Speed
Parameter Description
Min.
Max.
Min.
Max.
Units
Input Module Propagation Delays
tINYH
Pad to Y High
4.0
4.7
ns
tINYL
Pad to Y Low
3.6
4.3
ns
tINGH
G to Y High
6.9
8.1
ns
tINGL
G to Y Low
6.6
7.7
ns
Input Module Predicted Routing Delays1
tRD1
FO=1 Routing Delay
6.2
7.3
ns
tRD2
FO=2 Routing Delay
7.2
8.4
ns
tRD3
FO=3 Routing Delay
7.7
9.1
ns
tRD4
FO=4 Routing Delay
8.9
10.5
ns
tRD8
FO=8 Routing Delay
12.9
15.2
ns
Global Clock Network
tCKH
Input Low to High
FO = 32
FO = 384
13.3
17.9
15.7
21.1
ns
tCKL
Input High to Low
FO = 32
FO = 384
13.3
18.2
15.7
21.4
ns
tPWH
Minimum Pulse Width High
FO = 32
FO = 384
6.9
7.9
8.1
9.3
ns
tPWL
Minimum Pulse Width Low
FO = 32
FO = 384
6.9
7.9
8.1
9.3
ns
tCKSW
Maximum Skew
FO = 32
FO = 384
0.6
3.1
0.6
3.1
ns
tSUEXT
Input Latch External Setup
FO = 32
FO = 384
0.0
ns
tHEXT
Input Latch External Hold
FO = 32
FO = 384
8.6
13.8
8.6
13.8
ns
tP
Minimum Period
FO = 32
FO = 384
13.7
16.0
16.2
18.9
ns
fMAX
Maximum Frequency
FO = 32
FO = 384
73
63
62
53
MHz
Note:
1.
Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based
on actual routing delay measurements performed on the device prior to shipment. Optimization techniques may further reduce delays by 0
to 4 ns.
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