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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | A10V10B-VQG80C |
| 寤犲晢锛� | Microsemi SoC |
| 鏂囦欢闋佹暩(sh霉)锛� | 19/98闋� |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | IC FPGA 1200 GATES 80-VQFP COM |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 90 |
| 绯诲垪锛� | ACT™ 1 |
| LAB/CLB鏁�(sh霉)锛� | 295 |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 57 |
| 闁€鏁�(sh霉)锛� | 1200 |
| 闆绘簮闆诲锛� | 2.7 V ~ 3.6 V |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 宸ヤ綔婧害锛� | 0°C ~ 70°C |
| 灏佽/澶栨锛� | 80-TQFP |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 80-VQFP锛�14x14锛� |
绗�1闋�绗�2闋�绗�3闋�绗�4闋�绗�5闋�绗�6闋�绗�7闋�绗�8闋�绗�9闋�绗�10闋�绗�11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�绗�18闋�鐣�(d膩ng)鍓嶇19闋�绗�20闋�绗�21闋�绗�22闋�绗�23闋�绗�24闋�绗�25闋�绗�26闋�绗�27闋�绗�28闋�绗�29闋�绗�30闋�绗�31闋�绗�32闋�绗�33闋�绗�34闋�绗�35闋�绗�36闋�绗�37闋�绗�38闋�绗�39闋�绗�40闋�绗�41闋�绗�42闋�绗�43闋�绗�44闋�绗�45闋�绗�46闋�绗�47闋�绗�48闋�绗�49闋�绗�50闋�绗�51闋�绗�52闋�绗�53闋�绗�54闋�绗�55闋�绗�56闋�绗�57闋�绗�58闋�绗�59闋�绗�60闋�绗�61闋�绗�62闋�绗�63闋�绗�64闋�绗�65闋�绗�66闋�绗�67闋�绗�68闋�绗�69闋�绗�70闋�绗�71闋�绗�72闋�绗�73闋�绗�74闋�绗�75闋�绗�76闋�绗�77闋�绗�78闋�绗�79闋�绗�80闋�绗�81闋�绗�82闋�绗�83闋�绗�84闋�绗�85闋�绗�86闋�绗�87闋�绗�88闋�绗�89闋�绗�90闋�绗�91闋�绗�92闋�绗�93闋�绗�94闋�绗�95闋�绗�96闋�绗�97闋�绗�98闋�
26
AC T 1 T i m i ng C har a c t e r i st i c s (continued)
(W or s t - C as e M i l i t a r y Cond i t i o n s , V CC = 4.5 V, TJ = 1 25掳C)
鈥樷€�1鈥� Speed
鈥楽td鈥� Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
Global Clock Network
tCKH
Input Low to High
FO = 16
FO = 128
7.8
8.9
9.2
10.5
ns
tCKL
Input High to Low
FO = 16
FO = 128
10.3
11.2
12.1
13.2
ns
tPWH
Minimum Pulse Width High
FO = 16
FO = 128
10.4
10.9
12.2
12.9
ns
tPWL
Minimum Pulse Width Low
FO = 16
FO = 128
10.4
10.9
12.2
12.9
ns
tCKSW
Maximum Skew
FO = 16
FO = 128
1.9
2.9
2.2
3.4
ns
tP
Minimum Period
FO = 16
FO = 128
21.7
23.2
25.6
27.3
ns
fMAX
Maximum Frequency
FO = 16
FO = 128
46
44
40
37
MHz
TTL Output Module Timing1
tDLH
Data to Pad High
12.1
14.2
ns
tDHL
Data to Pad Low
13.8
16.3
ns
tENZH
Enable Pad Z to High
12.0
14.1
ns
tENZL
Enable Pad Z to Low
14.6
17.1
ns
tENHZ
Enable Pad High to Z
16.0
18.8
ns
tENLZ
Enable Pad Low to Z
14.5
17.0
ns
dTLH
Delta Low to High
0.09
0.11
ns/pF
dTHL
Delta High to Low
0.12
0.15
ns/pF
CMOS Output Module Timing1
tDLH
Data to Pad High
15.1
17.7
ns
tDHL
Data to Pad Low
11.5
13.6
ns
tENZH
Enable Pad Z to High
12.0
14.1
ns
tENZL
Enable Pad Z to Low
14.6
17.1
ns
tENHZ
Enable Pad High to Z
16.0
18.8
ns
tENLZ
Enable Pad Low to Z
14.5
17.0
ns
dTLH
Delta Low to High
0.16
0.18
ns/pF
dTHL
Delta High to Low
0.09
0.11
ns/pF
Notes:
1.
Delays based on 50 pF loading.
2.
SSO information can be found in the Simultaneously Switching Output Limits for Actel FPGAs application note at
http://www.actel.com/appnotes.
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| A1010B-1VQ80C | IC FPGA 1200 GATES 80-VQFP COM |
| A1010B-1VQG80C | IC FPGA 1200 GATES 80-VQFP COM |
| 5745175-1 | CONN BACKSHELL DB50 DIE CAST |
| 5745172-1 | CONN BACKSHELL DB15 DIE CAST |
| A1010B-2PQG100C | IC FPGA 1200 GATES 100-PQFP COM |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| A10V20 | 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:5V and 3.3V Families fully compatible with JEDEC specifications |
| A10V20B | 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:ACT 1 Series FPGAs |
| A10V20B-1CQ84B | 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:ACT 1 Series FPGAs |
| A10V20B-1CQ84C | 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:ACT 1 Series FPGAs |
| A10V20B-1CQ84I | 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:ACT 1 Series FPGAs |
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