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MC9S12DT256 Device User Guide — V03.03
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A.1.6 ESD Protection and Latch-up Immunity
All ESD testing is in conformity with CDF-AEC-Q100 Stress test qualification for Automotive Grade
Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body
Model (HBM), the Machine Model (MM) and the Charge Device Model.
A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification. Complete DC parametric and functional testing is performed per the applicable device
specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.
Table A-2 ESD and Latch-up Test Conditions
2. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply.
The absolute maximum ratings apply when the device is powered from an external source.
3. All digital I/O pins are internally clamped to V
SSX
and V
DDX
, V
SSR
and V
DDR
or V
SSA
and V
DDA
.
4. Those pins are internally clamped to V
SSPLL
and V
DDPLL
.
5. This pin is clamped low to V
SSR
, but not clamped high. This pin must be tied low in applications.
Model
Description
Symbol
Value
Unit
Human Body
Series Resistance
R1
1500
Ohm
Storage Capacitance
C
100
pF
Number of Pulse per pin
positive
negative
-
-
3
3
Machine
Series Resistance
R1
0
Ohm
Storage Capacitance
C
200
pF
Number of Pulse per pin
positive
negative
-
-
3
3
Latch-up
Minimum input voltage limit
-2.5
V
Maximum input voltage limit
7.5
V
Table A-3 ESD and Latch-Up Protection Characteristics
Num C
Rating
Symbol
Min
Max
Unit
1
C Human Body Model (HBM)
V
HBM
2000
-
V
2
C Machine Model (MM)
V
MM
200
-
V
3
C Charge Device Model (CDM)
V
CDM
500
-
V
4
C
Latch-up Current at T
A
= 125
°
C
positive
negative
I
LAT
+100
-100
-
mA
5
C
Latch-up Current at T
A
= 27
°
C
positive
negative
I
LAT
+200
-200
-
mA