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參數(shù)資料
| 型號： | 9S12C128DGV1 |
| 英文描述： | MC9S12C Family Device User Guide |
| 中文描述： | MC9S12C家庭設備用戶指南 |
| 文件頁數(shù)： | 72/136頁 |
| 文件大?。?/td> | 2190K |
| 代理商： | 9S12C128DGV1 |
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Device User Guide — 9S12C128DGV1/D V01.10
72
To prevent unnecessary current flow in production package options, the states of DDRK and PUPKE
should not be changed by software.
Section 7 Voltage Regulator (VREG) Block Description
Consult the VREG Block User Guide for information about the dual output linear voltage regulator.
7.1 Device-specific information
The VREG is part of the IPBus domain.
7.1.1 VREGEN
VREGEN is connected internally to VDDR.
7.1.2 VDD1, VDD2, VSS1, VSS2
In the 80 pin QFP package versions, both internal VDD and VSS of the 2.5V domain are bonded out on 2
sides of the device as two pin pairs (VDD1, VSS1 & VDD2, VSS2). VDD1 and VDD2 are connected
together internally. VSS1 and VSS2 are connected together internally.
The extra pin pair enables systems using the 80 pin package to employ better supply routing and further
decoupling.
Section 8 Recommended Printed Circuit Board Layout
The PCB must be carefully laid out to ensure proper operation of the voltage regulator as well as of the
MCU itself. The following rules must be observed:
Every supply pair must be decoupled by a ceramic capacitor connected as near as possible to the
corresponding pins (C1 - C6).
Central point of the ground star should be the VSSR pin.
Use low ohmic low inductance connections between VSS1, VSS2 and VSSR.
VSSPLL must be directly connected to VSSR.
Keep traces of VSSPLL, EXTAL and XTAL as short as possible and occupied board area for C7,
C8, C11 and Q1 as small as possible.
Do not place other signals or supplies underneath area occupied by C7, C8, C10 and Q1 and the
connection area to the MCU.
Central power input should be fed in at the VDDA/VSSA pins.
F
For More Information On This Product,
Go to: www.freescale.com
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