- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄360656 > 9S12C128DGV1 MC9S12C Family Device User Guide PDF資料下載
參數(shù)資料
| 型號(hào)： | 9S12C128DGV1 |
| 英文描述： | MC9S12C Family Device User Guide |
| 中文描述： | MC9S12C家庭設(shè)備用戶指南 |
| 文件頁(yè)數(shù)： | 61/136頁(yè) |
| 文件大?。?/td> | 2190K |
| 代理商： | 9S12C128DGV1 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)當(dāng)前第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)
61
2.3.14 PE1 / IRQ — Port E input Pin [1] / Maskable Interrupt Pin
The IRQ input provides a means of applying asynchronous interrupt requests to the MCU. Either falling
edge-sensitive triggering or level-sensitive triggering is program selectable (INTCR register). IRQ is
always enabled and configured to level-sensitive triggering out of reset. It can be disabled by clearing
IRQEN bit (INTCR register). When the MCU is reset the IRQ function is masked in the condition code
register. This pin is always an input and can always be read. There is an active pull-up on this pin while in
reset and immediately out of reset. The pull-up can be turned off by clearing PUPEE in the PUCR register.
2.3.15 PE0 / XIRQ — Port E input Pin [0] / Non Maskable Interrupt Pin
The XIRQ input provides a means of requesting a non maskable interrupt after reset initialization. During
reset, the X bit in the condition code register (CCR) is set and any interrupt is masked until MCU software
enables it. Because the XIRQ input is level sensitive, it can be connected to a multiple-source wired-OR
network. This pin is always an input and can always be read. There is an active pull-up on this pin while
in reset and immediately out of reset. The pull-up can be turned off by clearing PUPEE in the PUCR
register.
2.3.16 PAD[7:0] / AN[7:0] — Port AD I/O Pins [7:0]
PAD7-PAD0 are general purpose I/O pins and also analog inputs for the analog to digital converter. In
order to use a PAD pin as a standard input, the corresponding ATDDIEN register bit must be set. These
bits are cleared out of reset to configure the PAD pins for A/D operation.
When the A/D converter is active in multi-channel mode, port inputs are scanned and converted
irrespective of PortAD configuration. Thus PortAD pins that are configured as digital inputs or digital
outputs are also converted in the A/D conversion sequence.
2.3.17 PP[7] / KWP[7] — Port P I/O Pin [7]
PP7 is a general purpose input or output pin, shared with the keypad interrupt function. When configured
as an input, it can generate interrupts causing the MCU to exit STOP or WAIT mode. This pin is not
available in the 48 / 52 pin package versions.
2.3.18 PP[6] / KWP[6]/ROMCTL — Port P I/O Pin [6]
PP6 is a general purpose input or output pin, shared with the keypad interrupt function. When configured
as an input, it can generate interrupts causing the MCU to exit STOP or WAIT mode. This pin is not
available in the 48 / 52 pin package versions. During MCU expanded modes of operation, this pin is used
to enable the Flash EEPROM memory in the memory map (ROMCTL). At the rising edge of RESET, the
state of this pin is latched to the ROMON bit.
PP6=1 in emulation modes equates to ROMON =0 (ROM space externally mapped)
PP6=0 in expanded modes equates to ROMON =0 (ROM space externally mapped)
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 9S12D32DGV1 | 9S12DGDJ64DGV1 Device Guide. also covers 9S12D64. 9S12A64. 9S12D32. and 9S12A32 devices |
| 9S12DJ64DGV1 | 9S12DJ64DG Device Guide. also covers 9S12D64. 9S12A64. 9S12D32 and 9S12A32 devices |
| 9S12DJ64-ZIP_PART2 | MC9S12DJ64 Users Guides. zip format. part 2 |
| 9S12DP256BDGV2 | 9S12Dx256B Device Guide. also covers C derivatives and 9S12Ax256 devices |
| 9S12DP512DGV1 | 9S12Dx512 Device Guide |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 9S12D32DGV1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:9S12DGDJ64DGV1 Device Guide. also covers 9S12D64. 9S12A64. 9S12D32. and 9S12A32 devices |
| 9S12DJ64DGV1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:9S12DJ64DG Device Guide. also covers 9S12D64. 9S12A64. 9S12D32 and 9S12A32 devices |
| 9S12DP256BDGV1 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Automotive applications |
| 9S12DP256BDGV2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:9S12Dx256B Device Guide. also covers C derivatives and 9S12Ax256 devices |
| 9S12DP512DGV1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:9S12Dx512 Device Guide |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。