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參數(shù)資料
| 型號： | 9LPRS464YGLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產生/分配 |
| 英文描述： | 240 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封裝： | 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153N, TSSOP-56 |
| 文件頁數(shù)： | 13/23頁 |
| 文件大?。?/td> | 246K |
| 代理商： | 9LPRS464YGLFT |
20
ICS9LPRS464
System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUss
IDTTM/ICSTM
System Clock Chip for ATI RS/RD600 series chipsets using AMD CPUs
1377A—04/07/08
RESET_IN# - Assertion (transition from '1' to '0')
The pin is a Schmitt trigger input with debouncing. After it is triggered, REF clocks will wait for two clock cycle to
Asserting RESET_IN pin stops all the outputs including CPU, SRC, ATIG, PCI and USB with the REF[2:0] running.
be power down and re-power up, and SMBus will be reloaded. It will take no more than 2.5mS for the clocks to come
out with correct frequencies and no glitches.
** Deassertion of RESET_IN# (transition from '0' to '1') has NO effect on the clocks.
ensure the RESET_IN is asserted. Then, it will take 3uS for the clocks to stop without glitches. The clock chip will
2.5mS max
3 uS max
2 clock
cycles
RESET_IN#
REF [2:0]
*CLKS
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