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參數(shù)資料
| 型號： | 935268625551 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64 |
| 文件頁數(shù)： | 6/82頁 |
| 文件大小： | 1965K |
| 代理商： | 935268625551 |
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Philips Semiconductors
ISP1581
Hi-Speed USB interface device
Product data
Rev. 05 — 26 February 2003
14 of 78
9397 750 10766
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
7.8 DMA Interface and DMA Handler
The DMA block can be subdivided into two blocks: the DMA Handler and the DMA
Interface.
The rmware writes to the DMA Command register to start a DMA transfer (see
Table 28). The command opcode determines whether a generic DMA, PIO, MDMA or
UDMA transfer will start. The Handler interfaces to the same FIFO (internal RAM) as
used by the USB core. Upon receiving the DMA Command, the DMA Handler directs
the data from the internal RAM to the external DMA device or from the external DMA
device to the internal RAM.
The DMA Interface congures the timings and the DMA handshake. Data can be
transferred either using DIOR and DIOW strobes or by the DACK and DREQ
handshakes. The different DMA congurations are set up by writing to the DMA
Conguration register (see Table 33 and Table 34).
For an IDE-based storage interface, the applicable DMA modes are PIO (Parallel
I/O), MDMA (Multi word DMA; ATA), and UDMA (Ultra DMA; ATA).
For a generic DMA interface, the DMA modes that can be used are Generic DMA
(Slave) and MDMA (Master).
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