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| 型號(hào)： | 935268625551 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64 |
| 文件頁(yè)數(shù)： | 31/82頁(yè) |
| 文件大小： | 1965K |
| 代理商： | 935268625551 |
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Philips Semiconductors
ISP1581
Hi-Speed USB interface device
Product data
Rev. 05 — 26 February 2003
37 of 78
9397 750 10766
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
In 8-bit bus mode, the 16-bit Task File register 1F0 requires 2 consecutive write/read
accesses before the proper PIO write/read is generated on the IDE interface. The rst
byte is always the lower byte (LSByte). Other task le registers can be accessed
directly.
Writing to Task File registers can be done in any order except for Task File register
1F7, which must be written last.
Table 40:
ATAPI peripheral register addressing
Task le
CS1
CS0
DA2
DA1
DA0
1F0
H
LLLL
1F1
H
LLLH
1F2
H
L
H
L
1F3
H
L
H
1F4
HL
L
1F5
HL
H
1F6
HL
HHL
1F7
HL
HHH
3F6
L
HHHL
3F7
L
HHHH
Table 41:
Task File register 1F0 (address: 40H): bit allocation
CS1 = H, CS0 = L, DA2 = L, DA1 = L, DA0 = L.
Bit
7
6
5
4
3
2
1
0
Symbol
data (ATA or ATAPI)
Reset
00H
Bus reset
00H
Access
R/W
Table 42:
Task File register 1F1 (address: 48H): bit allocation
CS1 = H, CS0 = L, DA2 = L, DA1 = L, DA0 = H.
Bit
7
6
5
4
3
2
1
0
Symbol
error/feature (ATA or ATAPI)
Reset
00H
Bus reset
00H
Access
R/W
Table 43:
Task File register 1F2 (address: 49H): bit allocation
CS1 = H, CS0 = L, DA2 = L, DA1 = H, DA0 = L.
Bit
7
6
5
4
3
2
1
0
Symbol
sector count (ATA) or interrupt reason (ATAPI)
Reset
00H
Bus reset
00H
Access
R/W
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