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參數(shù)資料
| 型號： | 935268625551 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64 |
| 文件頁數(shù)： | 17/82頁 |
| 文件大?。?/td> | 1965K |
| 代理商： | 935268625551 |
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Philips Semiconductors
ISP1581
Hi-Speed USB interface device
Product data
Rev. 05 — 26 February 2003
24 of 78
9397 750 10766
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Remark: The buffer can be validated or cleared automatically by using the Buffer
Length register (see Table 21).
9.3.4
Buffer Length register (address: 1CH)
This 2-byte register determines the current packet size (DATACOUNT) of the indexed
endpoint FIFO. The bit allocation is given in Table 21.
The Buffer Length register is automatically loaded with the FIFO size, when the
Endpoint MaxPacketSize register is written (see Table 22). A smaller value can be
written when required. After a bus reset the Buffer Length register is made zero.
IN endpoint: When data transfer is performed in multiples of MaxPacketSize, the
Buffer Length register is not signicant. This register is useful only when transferring
data that is not a multiple of MaxPacketSize. The following two examples
demonstrate the signicance of the Buffer Length register.
Example 1: Consider that the transfer size is 512 bytes and the MaxPacketSize is
programmed as 64 bytes, the Buffer Length register need not be lled. This is
because the transfer size is a multiple of MaxPacketSize, and the MaxPacketSize
packets will be automatically validated because the last packet is also of
MaxPacketSize.
Example 2: Consider that the transfer size is 510 bytes and the MaxPacketSize is
programmed as 64 bytes, the Buffer Length register should be lled with 62 bytes just
before the MCU writes the last packet of 62 bytes. This ensures that the last packet,
which is a short packet of 62 bytes, is automatically validated.
This is only applicable to the PIO mode access.
OUT endpoint: The DATACOUNT value is automatically initialized to the number of
data bytes sent by the host on each ACK.
Remark: When using a 16-bit microprocessor bus, the last byte of an odd-sized
packet is output as the lower byte (LSByte).
Table 19:
Data Port register: bit allocation
Bit
15
14
13
12
11
10
9
8
Symbol
DATAPORT[15:8]
Reset
00H
Bus reset
00H
Access
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
DATAPORT[7:0]
Reset
00H
Bus reset
00H
Access
R/W
Table 20:
Data Port register: bit description
Bit
Symbol
Description
15 to 8
DATAPORT[15:8]
data (upper byte); not used in 8-bit bus mode
7 to 0
DATAPORT[7:0]
data (lower byte)
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