參數(shù)資料
型號(hào)： 935268625551
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝： 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁數(shù)： 14/82頁
文件大?。?/td> 1965K
代理商： 935268625551
Philips Semiconductors
ISP1581
Hi-Speed USB interface device
Product data
Rev. 05 — 26 February 2003
21 of 78
9397 750 10766
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
9.2.5
DMA Conguration register (address: 38H)
9.2.6
DMA Hardware register (address: 3CH)
9.3 Data ow registers
9.3.1
Endpoint Index register (address: 2CH)
The Endpoint Index register selects a target endpoint for register access by the
microcontroller. The register consists of 1 byte and the bit allocation is shown in
Table 14. The following registers are indexed:
Endpoint MaxPacketsize
Endpoint Type
Buffer Length
Data Port
Short Packet
Control Function.
For example, to access the OUT data buffer of endpoint 1 via the Data Port register,
the Endpoint Index register has to be written rst with 02H.
6
IEDMA
A logic 1 enables interrupt upon DMA status change detection.
5
IEHS_STA
A logic 1 enables interrupt upon detection of a High Speed
Status change.
4
IERESM
A logic 1 enables interrupt upon detection of a ‘resume’ state.
3
IESUSP
A logic 1 enables interrupt upon detection of a ‘suspend’ state.
2
IEPSOF
A logic 1 enables interrupt upon detection of a Pseudo SOF.
1
IESOF
A logic 1 enables interrupt upon detection of an SOF.
0
IEBRST
A logic 1 enables interrupt upon detection of a bus reset.
Table 13:
Interrupt Enable register: bit description…continued
Bit
Symbol
Description
Table 14:
Endpoint Index register: bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
reserved
EP0SETUP
ENDPIDX[3:0]
DIR
Reset
-
0
00H
0
Bus reset
unchanged
Access
R/W
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