參數(shù)資料
型號: 935267395551
廠商: NXP SEMICONDUCTORS
元件分類: 顏色信號轉換
英文描述: COLOR SIGNAL DECODER, PBGA156
封裝: 15 X 15 MM, 1.15 MM HEIGHT, PLASTIC, MS-034, SOT-472-1, BGA-156
文件頁數(shù): 31/178頁
文件大?。?/td> 988K
代理商: 935267395551
2004 Jul 22
126
Philips Semiconductors
Product specication
Multistandard video decoder with adaptive
comb lter and component video input
SAA7118
15.2.19 SUBADDRESS 12H
Table 57 RT signal control: RTS0 output; 12H[3:0]
The polarity of any signal on RTS0 can be inverted via RTP0[11H[3]].
Note
1. Function of HL is selectable via HLSEL[13H[3]]:
a) HLSEL = 0: HL is standard horizontal lock indicator.
b) HLSEL = 1: HL is fast horizontal lock indicator (use is not recommended for sources with unstable timebase e.g.
VCRs).
RTS0 OUTPUT
RTSE03 RTSE02 RTSE01 RTSE00
3-state
0000
Constant LOW
0
1
CREF (13.5 MHz toggling pulse; see Fig.30)
0
1
0
CREF2 (6.75 MHz toggling pulse; see Fig.30)
0
1
HL; horizontal lock indicator (note 1):
0
1
0
HL = 0: unlocked
HL = 1: locked
VL; vertical and horizontal lock:
0
1
0
1
VL = 0: unlocked
VL = 1: locked
DL; vertical and horizontal lock and colour detected:
0
1
0
DL = 0: unlocked
DL = 1: locked
Reserved
0
1
HREF, horizontal reference signal; indicates 720 pixels valid data on the
expansion port. The positive slope marks the beginning of a new active
line. HREF is also generated during the vertical blanking interval
1000
HS:
1001
programmable width in LLC8 steps via HSB[7:0] 06H[7:0] and HSS[7:0]
07H[7:0]
fine position adjustment in LLC2 steps via HDEL[1:0] 11H[5:4]
(see Fig.30)
HQ; HREF gated with VGATE
1
0
1
0
Reserved
1
0
1
V123; vertical sync (see vertical timing diagrams Figs 28 and 29)
1
0
VGATE; programmable via VSTA[8:0] 17H[0] 15H[7:0], VSTO[8:0] 17H[1]
16H[7:0] and VGPS[17H[2]]
1101
LSBs of the 9-bit ADC’s
1
0
FID; position programmable via VSTA[8:0] 17H[0] 15H[7:0]; see vertical
timing diagrams Figs 28 and 29
1111
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