
2004
Jul
22
97
Philips
Semiconductors
Product
speci
cation
Multistandard
video
decoder
with
adaptiv
e
comb
lter
and
component
video
input
SAA7118
2004
Jul
22
97
Philips
Semiconductors
Product
speci
cation
Multistandard
video
decoder
with
adaptiv
e
comb
lter
and
component
video
input
SAA7118
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Reserved
37
Clock ratio AMXCLK to ASCLK
38
SDIV5
SDIV4
SDIV3
SDIV2
SDIV1
SDIV0
Clock ratio ASCLK to ALRCLK
39
LRDIV5
LRDIV4
LRDIV3
LRDIV2
LRDIV1
LRDIV0
Audio clock generator basic
setup
3A
APLL
AMVR
LRPH
SCPH
Reserved
3B to 3F
General purpose VBI data slicer part: registers 40H to 7FH
Slicer control 1
40
HAM_N
FCE
HUNT_N
LCR2 to LCR24 (n = 2 to 24)
41 to 57
LCRn_7
LCRn_6
LCRn_5
LCRn_4
LCRn_3
LCRn_2
LCRn_1
LCRn_0
Programmable framing code
58
FC7
FC6
FC5
FC4
FC3
FC2
FC1
FC0
Horizontal offset for slicer
59
HOFF7
HOFF6
HOFF5
HOFF4
HOFF3
HOFF2
HOFF1
HOFF0
Vertical offset for slicer
5A
VOFF7
VOFF6
VOFF5
VOFF4
VOFF3
VOFF2
VOFF1
VOFF0
Field offset and MSBs for
horizontal and vertical offset
5B
FOFF
RECODE
VOFF8
HOFF10
HOFF9
HOFF8
Reserved (for testing)
5C
Header and data identication
(DID) code control
5D
FVREF
DID5
DID4
DID3
DID2
DID1
DID0
Sliced data identication (SDID)
code
5E
SDID5
SDID4
SDID3
SDID2
SDID1
SDID0
Reserved
5F
Slicer status byte 0 (read only)
60
FC8V
FC7V
VPSV
PPV
CCV
Slicer status byte 1 (read only)
61
F21_N
LN8
LN7
LN6
LN5
LN4
Slicer status byte 2 (read only)
62
LN3
LN2
LN1
LN0
DT3
DT2
DT1
DT0
Reserved
63 to 7F
X port, I port and the scaler part: registers 80H to EFH
TASK INDEPENDENT GLOBAL SETTINGS: 80H TO 8FH
Global control 1
80
SMOD
TEB
TEA
ICKS3
ICKS2
ICKS1
ICKS0
Reserved
81 and
82
X port I/O enable and output
clock phase control
83
XPCK1
XPCK0
XRQT
XPE1
XPE0
REGISTER FUNCTION
SUB
ADDR.
(HEX)
D7
D6
D5
D4
D3
D2
D1
D0