參數(shù)資料
型號： 935267395518
廠商： NXP SEMICONDUCTORS
元件分類： 顏色信號轉換
英文描述： COLOR SIGNAL DECODER, PBGA156
封裝： 15 X 15 MM, 1.15 MM HEIGHT, PLASTIC, MS-034, SOT-472-1, BGA-156
文件頁數(shù)： 92/178頁
文件大?。?/td> 988K
代理商： 935267395518
2004 Jul 22
20
Philips Semiconductors
Product specication
Multistandard video decoder with adaptive
comb lter and component video input
SAA7118
8.1.1.1
Clamping
The clamp control circuit controls the correct clamping of
the analog input signals. The coupling capacitor is also
used to store and filter the clamping voltage. An internal
digital clamp comparator generates the information with
respect to clamp-up or clamp-down. The clamping levels
for the four ADC channels are fixed for luminance (120),
chrominance (256) and for component inputs as
component Y (32), components PB and PR (256) or
components RGB (32). Clamping time in normal use is set
with the HCL pulse on the back porch of the video signal.
8.1.1.2
Gain control
The gain control circuit receives (via the I2C-bus) the static
gain levels for the four analog amplifiers or controls one of
these amplifiers automatically via a built-in Automatic Gain
Control (AGC) as part of the Analog Input Control (AICO).
The AGC (automatic gain control for luminance) is used to
amplify a CVBS or Y signal to the required signal
amplitude, matched to the ADCs input voltage range.
Component inputs are gain adjusted manually at a fixed
gain. The AGC active time is the sync bottom of the video
signal.
Signal (white) peak control limits the gain at signal
overshoots. The flow charts (see Figs 9 and 10) show
more details of the AGC. The influence of supply voltage
variation within the specified range is automatically
eliminated by clamp and automatic gain control.
handbook, halfpage
HCL
MHB726
HSY
analog line blanking
TV line
1
120
511
GAIN
CLAMP
Fig.6
Analog line with clamp (HCL) and gain
range (HSY).
Fig.7 Automatic gain range.
analog input level
controlled
ADC input level
maximum
minimum
range 9 dB
0 dB
MHB325
+3 dB
6 dB
(1 V (p-p) 18/56
)
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