參數資料
型號： 935267395518
廠商： NXP SEMICONDUCTORS
元件分類： 顏色信號轉換
英文描述： COLOR SIGNAL DECODER, PBGA156
封裝： 15 X 15 MM, 1.15 MM HEIGHT, PLASTIC, MS-034, SOT-472-1, BGA-156
文件頁數： 125/178頁
文件大?。?/td> 988K
代理商： 935267395518
2004
Jul
22
50
Philips
Semiconductors
Product
speci
cation
Multistandard
video
decoder
with
adaptiv
e
comb
lter
and
component
video
input
SAA7118
2004
Jul
22
50
Philips
Semiconductors
Product
speci
cation
Multistandard
video
decoder
with
adaptiv
e
comb
lter
and
component
video
input
SAA7118
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With OFIDC = 0, the scalers input field ID is available as output field ID on bit D6 of SAV and EAV, respectively on pin IGP0 (IGP1), if FID output is
selected.
When OFIDC[90H[6]] = 1, the TOGGLE information is available as output field ID on bit D6 of SAV and EAV, respectively on pin IGP0 (IGP1), if FID
output is selected.
Additionally the bit D7 of SAV and EAV can be defined via CONLH[90H[7]]. CONLH[90H[7]] = 0 (default) sets D7 to logic 1, a logic 1 inverts the
SAV/EAV bit D7. So it is possible to mark the output of the both tasks by different SAV/EAV codes. This bit can also be seen as ‘task flag’ on the
pins IGP0 (IGP1), if TASK output is selected.
Table 10 Examples for eld processing
Notes
1. Single task every field; OFIDC = 0; subaddress 90H at 40H; TEB[80H[5]] = 0.
2. Tasks are used to scale to different output windows, priority on task B after SWRST.
3. Both tasks at 1
2 frame rate; OFIDC = 0; subaddresses 90H at 43H and C0H at 42H.
4. In examples 3 and 4 the association between input FID and tasks can be flipped, dependent on which time the SWRST is de-asserted.
5. Task B at 2
3 frame rate constructed from neighbouring motion phases; task A at
1
3 frame rate of equidistant motion phases; OFIDC = 1;
subaddresses 90H at 41H and C0H at 45H.
6. Task A and B at 1
3 frame rate of equidistant motion phases; OFIDC = 1; subaddresses 90H at 41H and C0H at 49H.
7. State of prior field.
8. It is assumed that input/output FID = 0 (= upper lines); UP = upper lines; LO = lower lines.
9. O = data output; NO = no output.
SUBJECT
FIELD SEQUENCE FRAME/FIELD
EXAMPLE 1(1)
EXAMPLE 2(2)(3)
EXAMPLE 3(2)(4)(5)
EXAMPLE 4(2)(4)(6)
1/1
1/2
2/1
1/1
1/2
2/1
2/2
1/1
1/2
2/1
2/2
3/1
3/2
1/1
1/2
2/1
2/2
3/1
3/2
Processed by task
A
B
A
B
A
B
ABBA
B
A
B
A
State of detected
ITU 656 FID
0
1
0
0101010101
0
1
0
1
01
TOGGLE ag
1
0
1
1100101100
11
00
Bit D6 of SAV/EAV byte
0
1
0
101101100
11
00
Required sequence
conversion at the vertical
scaler(8)
UP
↓
UP
LO
↓
LO
UP
↓
UP
↓
UP
LO
↓
LO
UP
↓
UP
LO
↓
LO
UP
↓
LO
↓
UP
↓
LO
↓
LO
UP
↓
UP
LO
↓
UP
↓
UP
LO
↓
LO
UP
↓
LO
↓
LO
UP
↓
UP
LO
↓
UP
Output(9)
O
OOOOOOOOOO
NO
OO
NO
OO
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