參數(shù)資料
型號(hào)： 935238950551
廠商： NXP SEMICONDUCTORS
元件分類： 數(shù)字傳輸電路
英文描述： CLOCK RECOVERY CIRCUIT, PQFP48
封裝： PLASTIC, SOT-313, LQFP-48
文件頁(yè)數(shù)： 4/26頁(yè)
文件大?。?/td> 335K
代理商： 935238950551
1998 Feb 09
12
Philips Semiconductors
Objective specication
SDH/SONET data and clock recovery unit
STM1/4 OC3/12
TZA3004HL
Notes
1. Typical supply voltage for the voltage regulator is
4.5 V (see Fig.4).
2. It is assumed that both CML inputs carry a complementary signal with the specified peak-to-peak value. (true
differential excitation)
3. The specified input voltage range is the guaranteed and tested range for proper operation; BER <10-10.
4. An input sensitivity for BER <10-10 of 7 mVpp is guaranteed. Typical input sensitivity for BER <10-10 is 2.5mVpp.
5. CML inputs are terminated internally using 50
on-chip resistors to ground (GND).
6. Output voltage range with default reference voltage on AREF (floating pin).
7. Output voltage range with adjustment of voltage on AREF (see section “Output amplitude reference (AREF)”).
8. Data to clock delay according to figure 7. Measured with 1010 data pattern, single ended output signals and rising
edge of COUT to DOUT or CLOOP to DLOOP. Note that small deviations from specified value are possible if
differentially measured.
9. External 10 k
pull-up resistor to +3.3 V.
10. LOS assert/de-assert timing and BER level are for indication only. The values are neither production tested nor
guaranteed.
11. Measured according ITU specification G.958 on the OM5800 STM4 demoboard.
12. TDR is bitrate independent.
ta
LOS assert time
note 10
0.1
s
td
LOS de-assert time
10
s
BERLOS
LOS assert Bit Error Rate
5 102
BER
LOS de-assert Bit Error Rate
1 103
BER
PLL Characteristics
tacq
acquisition time
CREF = 19.44 MHz
50
200
s
CREF = 38.88 MHz
100
200
s
Jtol(p-p)(5)
jitter tolerance (peak-to-peak)
STM1/OC3 mode
f = 6.5 kHz
1.5
>5
UI
f = 65 kHz
0.15
1.3
UI
f = 1 MHz
0.15
0.8
UI
STM4/OC12 mode
f = 25 kHz
1.5
>5
UI
f = 100 kHz
0.7
3
UI
f = 250 kHz
0.15
1.3
UI
f = 1 MHz
0.15
0.50
UI
f = 5 MHz
0.15
0.35
UI
TDR
transitionless data run
note 6
2000
bits
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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