
1998 Feb 09
4
Philips Semiconductors
Objective specication
SDH/SONET data and clock recovery unit
STM1/4 OC3/12
TZA3004HL
PINNING
SYMBOL
PIN
DESCRIPTION
ENL
1
loop mode enable input (active low)
GND
2
ground
CLOOP
3
clock output in loop mode (differential)
CLOOPQ
4
inverted clock output in loop mode (differential)
GND
5
ground
DLOOP
6
data output in loop mode (differential)
DLOOPQ
7
inverted data output in loop mode (differential)
GND
8
ground
REF19
9
reference frequency select input (see Table 2)
GND
10
ground
GND
11
ground
LOCK
12
phase lock detection output
i.c
13
internally connected (leave open)
GND
14
ground
CAPUPQ
15
external loop lter capacitor
CAPDOQ
16
external loop lter capacitor return
GND
17
ground
i.c.
18
internally connected (leave open)
i.c.
19
internally connected (leave open)
GND
20
ground
CREF
21
reference clock input (differential)
CREFQ
22
inverting reference clock input (differential)
GND
23
ground
REF39
24
reference frequency select input (see Table 2)
VEE
25
negative supply voltage
GND
26
ground
VEE
27
negative supply voltage
VEE
28
negative supply voltage
GND
29
ground
SEL155
30
STM mode select input (see Table 1)
VEE
31
negative supply voltage
GND
32
ground
DIN
33
data input (differential)
DINQ
34
inverting data input (differential)
GND
35
ground
i.c.
36
internally connected (leave open)
PC
37
negative power supply control signal output
GND
38
ground
LOS
39
loss-of-signal detection output
i.c.
40
internally connected (leave open)