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參數(shù)資料
| 型號(hào)： | 9248YF-195LF-T |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 140 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | 0.300 INCH, LEAD FREE, MO-118, SSOP-48 |
| 文件頁(yè)數(shù)： | 6/15頁(yè) |
| 文件大?。?/td> | 158K |
| 代理商： | 9248YF-195LF-T |
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ICS9248-195
0375E—12/15/08
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9248-195. It is used to turn off the PCICLK clocks for low power
operation. PCI_STOP# is synchronized by the ICS9248-195 internally. The minimum that the PCICLK clocks are
enabled (PCI_STOP# high pulse) is at least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started
with a full high pulse width guaranteed. PCICLK clock on latency cycles are only three rising PCICLK clocks, off latency
is one PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9248.
3. All other clocks continue to run undisturbed.
4. CLK_STOP# is shown in a high (true) state.
CPUCLK
(Internal)
PCICLK_F
(Internal)
PCICLK_F
(Free-running)
CLK_STOP#
PCICLK
PCI_STOP#
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