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參數(shù)資料
| 型號(hào)： | 9248YF-20LF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | 0.300 INCH, ROHS COMPLIANT, MO-118, SSOP-48 |
| 文件頁(yè)數(shù)： | 1/12頁(yè) |
| 文件大?。?/td> | 181K |
| 代理商： | 9248YF-20LF |
Integrated
Circuit
Systems, Inc.
General Description
Features
ICS9248-20
0276E—12/15/08
Block Diagram
Pentium/ProTM System Clock Chip
Pin Configuration
48-Pin SSOP
Generates system clocks for CPU, IOAPIC, PCI,
plus 14.314 MHz REF (0:2), USB, and Super I/O
Supports single or dual processor systems
Supports Spread Spectrum modulation for CPU &
PCI clocks, down spread -0.5%
Skew from CPU (earlier) to PCI clock (rising edges
for 100/33.3MHz) 1.5 to 4ns
Two fixed outputs at 48MHz.
Separate 2.5V and 3.3V supply pins
2.5V or 3.3V output: CPU, IOAPIC
3.3V outputs: PCI, REF, 48MHz
No power supply sequence requirements
Uses external 14.318MHz crystal, no external load
cap required for CL=18pF crystal
48 pin 300 mil SSOP
The ICS9248-20 is a Clock Synthesizer chip for Pentium
and PentiumPro CPU based Desktop/Notebook systems
that will provide all necessary clock timing.
Features include four CPU and eight PCI clocks. Three
reference outputs are available equal to the crystal
frequency. Additionally, the device meets the Pentium
power-up stabilization requirement, assuring that CPU
and PCI clocks are stable within 2ms after power-up.
PD# pin enables low power mode by stopping crystal OSC
and PLL stages. Other power management features
include CPU_STOP#, which stops CPU (0:3) clocks, and
PCI_STOP#, which stops PCICLK (0:6) clocks.
High drive CPUCLK outputs typically provide greater than
1 V/ns slew rate into 20pF loads. PCICLK outputs typically
provide better than 1V/ns slew rate into 30pF loads while
maintaining 50±5% duty cycle. The REF clock outputs
typically provide better than 0.5V/ns slew rates.
The ICS9248-20 accepts a 14.318MHz reference crystal
or clock as its input and runs on a 3.3V core supply.
Power Groups
VDD = Supply for PLL core
VDD1 = REF (0:2), X1, X2
VDD2 = PCICLK_F, PCICLK (0:6)
VDD3 = 48MHz0, 48MHz1
VDDL1 = IOAPIC (0:1)
VDDL2 = CPUCLK (0:3)
Ground Groups
GND = Ground for PLL core
GND1 = REF (0:2), X1, X2
GND2 = PCICLK_F, PCICLK (0:6)
GND3 = 48MHz0, 48MHz1
GNDL1 = IOAPIC (0:1)
GNDL2 = CPUCLK (0:3)
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