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參數(shù)資料
| 型號(hào)： | 9248YF-195LF-T |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類(lèi)： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 140 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | 0.300 INCH, LEAD FREE, MO-118, SSOP-48 |
| 文件頁(yè)數(shù)： | 5/15頁(yè) |
| 文件大小： | 158K |
| 代理商： | 9248YF-195LF-T |
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ICS9248-195
0375E—12/15/08
CLK_STOP# Timing Diagram
CLK_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power
operation.CLK_STOP# is synchronized by the ICS9248-195.The minimum that the CPU clock is enabled (CLK_STOP#
high pulse) is 100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled.The CPU clocks
will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse.
CPU clock on latency is less than 4 CPU clocks and CPU clock off latency is less than 4 CPU clocks.
Notes:
1. All timing is referenced to the internal CPU clock.
2. CLK_STOP# is an asynchronous input and metastable conditions may exist. This signal is
synchronized to the CPU clocks inside the ICS9248-195.
3. SDRAM-F output is controlled by Buffer in signal, not affected by the ICS9248-195
CLK_STOP# signal. SDRAM are controlled as shown.
4. All other clocks continue to run undisturbed.
PCICLK
SDRAM
CPUCLK
CPUCLK _F
SDRAM_F
PCI_STOP# (High)
CLK_STOP#
INTERNAL
CPUCLK
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