參數(shù)資料
型號(hào)： 9248AG-192T
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時(shí)鐘產(chǎn)生/分配
英文描述： 66.6 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28
封裝： 4.40 MM, 0.65 MM PITCH, MO-153, TSSOP-28
文件頁(yè)數(shù)： 8/15頁(yè)
文件大?。?/td> 201K
代理商： 9248AG-192T
2
ICS9248-192
0540F—10/27/05
Pin Descriptions
Pin number
Pin name
Type
Description
1
GNDREF
Power
Ground for 14.318 MHz reference clock outputs
2
X1
Input
14.318 MHz crystal input
3
X2
Output
14.318 MHz crystal output
4PD#
Input
Asynchronous active low input pin used to power down the device
into a low power state. The internal clocks are disabled and the
VCO and the crystal are stopped. The latency of the power down
will not be greater than 3ms.
12, 11, 10, 7, 6, 5
PCICLK (5:0)
Output
3.3V PCI clock outputs, free running selectable
8
GNDPCI
Power
Ground for PCI clock outputs
9
VDDPCI
Power
3.3V power for the PCI clock outputs
Sel48_24#
Input
Selects 24MHz (0) or 48MHz (1) output
24_48MHz
Output
Selectable output either 24MHz or 48MHz
13
SDATA
I/O
Data pin for I
2C circuitry 5V tolerant
14
SCLK
IN
Clock pin of I
2C circuitry 5V tolerant
CPU3.3-2.5#
Input
3.3 (1) or 2.5 (0) VDD buffer strength selection, has pullup to VDD,
nominal 30K resistor.
48MHz
Output
3.3V 48 MHz clock output, fixed frequency clock typically used with
USB devices
17
GND48
Power
Ground for 48 MHz clocks
18
VDD48
Power
3.3V power for 48/24 MHz clocks
19
SEL 66/60#
Input
Control for the frequency of clocks at the
CPU & PCICLK output pins.
"0" = 60 MHz. "1" = 66.6 MHz.
The PCI clock is multiplexed to run at 33.3 MHz
for both selected cases.
20
VDD_Core
Power
Isolated 3.3V power for core
21
GND_Core
Power
Isolated ground for core
22
PCI_Stop#
Input
Synchronous active low input used to stop the PCICLK in active low
state. It will not effect PCICLK_F or any other outputs.
23
CPUCLK0
Output
CPU clock outputs selectable 2.5V or 3.3V.
24
GNDLCPU
Power
Ground for CPU clock outputs
25
VDDLCPU
Power
2.5V or 3.3V power for CPU clock outputs
26
CPU_STOP#
Input
Asynchronous active low input pin used to stop the CPUCLK in
active low state, all other clocks will continue to run. The CPUCLK
will have a "Turnon " latency of at least 3 CPU clocks.
27
REF
Output
3.3V 14.318 MHz reference clock output
28
VDDREF
Power
3.3V power for 14.318 MHz reference clock outputs.
15
16
相關(guān)PDF資料
PDF描述
9248AG-192LF 66.6 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28
9248AG-192 66.6 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28
051-453-0000 RF Coaxial Connectors
9248AG-92LFT 100 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
9248BF-138 166.67 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
9248AG-198LF 制造商:Integrated Device Technology Inc 功能描述:9248AG-198LF - Bulk
9248AG-92LF 制造商:Integrated Device Technology Inc 功能描述:PLL CLOCK GEN DUAL 48TSSOP - Rail/Tube
9248AG-92LFT 制造商:Integrated Device Technology Inc 功能描述:9248AG-92LFT - Tape and Reel
9248BF-195LF 制造商:Integrated Device Technology Inc 功能描述:PLL FREQ GENERATOR DUAL 48SSOP - Bulk
9248BF-81LF 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
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