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參數(shù)資料
| 型號(hào)： | 9248AG-192T |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類(lèi)： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 66.6 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28 |
| 封裝： | 4.40 MM, 0.65 MM PITCH, MO-153, TSSOP-28 |
| 文件頁(yè)數(shù)： | 13/15頁(yè) |
| 文件大小： | 201K |
| 代理商： | 9248AG-192T |
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ICS9248-192
0540F—10/27/05
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9248-192. It is used to turn off the PCICLK clocks for low power
operation. PCI_STOP# is synchronized by the ICS9248-192 internally. The minimum that the PCICLK clocks are
enabled (PCI_STOP# high pulse) is at least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started
with a full high pulse width guaranteed. PCICLK clock on latency cycles are only one rising PCICLK clock off latency
is one PCICLK clock.
CPU_STOP# Timing Diagram
CPUSTOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation.
CPU_STOP# is synchronized by the ICS9248-192.The minimum that the CPUCLK is enabled (CPU_STOP# high pulse)
is 100 CPUCLKs. All other clocks will continue to run while the CPUCLKs are disabled. The CPUCLKs will always be
stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPUCLK on latency
is less than 4 CPUCLKs and CPUCLK off latency is less than 4 CPUCLKs.
Notes:
1. All timing is referenced to the internal CPUCLK.
2. CPU_STOP# is an asynchronous input and metastable conditions may
exist. This signal is synchronized to the CPUCLKs inside the ICS9248-192.
3. All other clocks continue to run undisturbed.
4. PD# and PCI_STOP# are shown in a high (true) state.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248-192 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9248-192.
3. All other clocks continue to run undisturbed.
4. PD# and CPU_STOP# are shown in a high (true) state.
PCICLK
CPUCLK
PCI_STOP# (High)
CPU_STOP#
PD# (High)
INTERNAL
CPUCLK
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| 9248AG-192LF | 66.6 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 9248AG-198LF | 制造商:Integrated Device Technology Inc 功能描述:9248AG-198LF - Bulk |
| 9248AG-92LF | 制造商:Integrated Device Technology Inc 功能描述:PLL CLOCK GEN DUAL 48TSSOP - Rail/Tube |
| 9248AG-92LFT | 制造商:Integrated Device Technology Inc 功能描述:9248AG-92LFT - Tape and Reel |
| 9248BF-195LF | 制造商:Integrated Device Technology Inc 功能描述:PLL FREQ GENERATOR DUAL 48SSOP - Bulk |
| 9248BF-81LF | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類(lèi)型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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