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參數(shù)資料
| 型號(hào)： | 908E626 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | Integrated Stepper Motor Driver with Embedded MCU and LIN Serial Communication |
| 中文描述： | 集成的步進(jìn)電機(jī)驅(qū)動(dòng)器，帶有嵌入式微控制器和LIN串行通信 |
| 文件頁數(shù)： | 28/32頁 |
| 文件大小： | 303K |
| 代理商： | 908E626 |
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908E626
28
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
HB_OCF—H-Bridge Overcurrent Flag Bit
This read/write flag is set on an overcurrent condition at the
H-Bridges. Clear HB_OCF and enable the H-Bridge driver by
writing a logic [1] to HB_OCF. Reset clears the HB_OCF bit.
Writing a logic [0] to HB_OCF has no effect.
1 = Overcurrent condition on H-Bridges has occurred.
0 = No overcurrent condition on H-Bridges has occurred.
HTF—Overtemperature Status Bit
This read-only bit is a copy of the HTF bit in the Interrupt Flag
Register.
1 = Overtemperature condition has occurred.
0 = No overtemperature condition has occurred.
Autonomous Watchdog (AWD)
The Autonomous Watchdog module allows to protect the
CPU against code runaways.
The AWD is enabled if AWDRE in the AWDCTL Register is
set. If this bit is cleared, the AWD oscillator is disabled and the
watchdog switched off.
Watchdog
The watchdog function is only available in RUN mode. On
setting the AWDRE bit, watchdog functionality in RUN mode is
activated. Once this function is enabled, it is not possible to
disable it via software.
If the timer reaches end value and AWDRE is set, a system
reset is
initiated. Operations of the watchdog function cease in
STOP mode. Normal operation will be continued when the
system is back to RUN mode.
To prevent a watchdog reset, the watchdog timeout counter
must be reset before it reaches the end value. This is done by
a write to the AWDRST bit in the AWDCTL Register.
Autonomous Watchdog Control Register (AWDCTL)
AWDRST—Autonomous Watchdog Reset Bit
This write-only bit resets the Autonomous Watchdog timeout
period. AWDRST always reads 0. Reset clears AWDRST bit.
1 = Reset AWD and restart timeout period.
0 = No effect.
AWDRE—Autonomous Watchdog Reset Enable Bit
This read/write bit enables resets on AWD timeouts. A reset
on the
RST_A
is asserted when the Autonomous Watchdog has
reached the timeout and the Autonomous Watchdog is
enabled. AWDRE is one-time setable (write once) after each
reset. Reset clears the AWDRE bit.
1 = Autonomous watchdog enabled.
0 = Autonomous watchdog disabled.
AWDR—Autonomous Watchdog Rate Bit
This read/write bit selects the clock rate of the Autonomous
Watchdog. Reset clears the AWDR bit.
1 = Fast rate selected (10 ms).
0 = Slow rate selected (20 ms).
Voltage Regulator
The 908E626 chip contains a low-power, low-drop voltage
regulator to provide internal power and external power for the
MCU. The V
DD
regulator accepts a unregulated input supply
and provides a regulated V
DD
supply to all digital sections of the
device. The output of the regulator is also connected to the VDD
terminal to provide the 5.0 V to the microcontroller.
Register Name and Address: AWDCTL - $0a
Bit7
6
5
4
3
2
1
Bit0
Read
0
0
0
AWDRE
0
(Note 17)
0
(Note 17)
0
AWDR
Write
AWDRST
Reset
0
0
0
0
0
0
0
0
Notes
19.
This bit must always be set to 0.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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| 908E626_08 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated Stepper Motor Driver with Embedded MCU and LIN Serial Communication |
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