參數(shù)資料
型號(hào): 908E624
廠商: Motorola, Inc.
英文描述: TRIPLE HIGH-SIDE SWITCH WITH EMBEDDED MCU AND LIN
中文描述: 三重高邊開關(guān)與嵌入式微控制器和LIN
文件頁(yè)數(shù): 12/32頁(yè)
文件大小: 453K
代理商: 908E624
Analog Integrated Circuit Device Data
Freescale Semiconductor
12
908E624
Dynamic Electrical Characteristics
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
All characteristics are for the analog chip only. Please refer to the 68HC908EY16 datasheet for characteristics of the
microcontroller chip. Characteristics noted under conditions 9.0 V
V
SUP
16 V, -40
°
C
T
J
125
°
C unless otherwise noted.
Typical values noted reflect the approximate parameter mean at T
A
= 25
°
C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
LIN Physical Layer
Driver Characteristics for Normal Slew Rate
(21)
,
(22)
Dominant Propagation Delay TXD to LIN
t
DOM-
MIN
50
μ
s
Dominant Propagation Delay TXD to LIN
t
DOM-
MAX
50
μ
s
Recessive Propagation Delay TXD to LIN
t
REC-
MIN
50
μ
s
Recessive Propagation Delay TXD to LIN
t
REC-
MAX
50
μ
s
Propagation Delay Symmetry: t
DOM-MIN
- t
REC-
MAX
dt1
-10.44
μ
s
Propagation Delay Symmetry: t
DOM-
MAX
- t
REC-
MIN
Driver Characteristics for Slow Slew Rate
(21)
,
(23)
dt2
11
μ
s
Dominant Propagation Delay TXD to LIN
t
DOM-
MIN
100
μ
s
Dominant Propagation Delay TXD to LIN
t
DOM-
MAX
100
μ
s
Recessive Propagation Delay TXD to LIN
t
REC-
MIN
100
μ
s
Recessive Propagation Delay TXD to LIN
t
REC-
MAX
100
μ
s
Propagation Delay Symmetry: t
DOM-
MIN
- t
REC-
MAX
dt1s
-22
μ
s
Propagation Delay Symmetry: t
DOM-MAX
- t
REC-
MIN
dt2s
23
μ
s
Driver Characteristics for Fast Slew Rate
LIN High Slew Rate (Programming Mode)
SR
FAST
15
V/
μ
s
Receiver Characteristics and Wake-Up Timings
Receiver Dominant Propagation Delay
(24)
t
RL
3.5
6.0
μ
s
Receiver Recessive Propagation Delay
(24)
t
RH
3.5
6.0
μ
s
Receiver Propagation Delay Symmetry
t
R-SYM
-2.0
2.0
μ
s
Bus Wake-Up Deglitcher
t
PROP
WL
35
80
μ
s
Bus Wake-Up Event Reported
(25)
t
WAKE
20
μ
s
Notes
21.
V
SUP
from 7.0 V to 18 V, bus load R0 and C0 1.0 nF/1.0 k
, 6.8 nF/660
, 10 nF/500
. Measurement thresholds: 50% of TXD signal
to LIN signal threshold defined at each parameter.
See
Figure 6
, page
15
.
See
Figure 7
, page
16
.
Measured between LIN signal threshold V
IL
or V
IH
and 50% of RXD signal.
t
WAKE
is typically 2 internal clock cycles after LIN rising edge detected. See
Figure 8
and
Figure 9
, page
16
. In Sleep mode the V
DD
rise time is strongly dependent upon the decoupling capacitor at VDD terminal.
22.
23.
24.
25.
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