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參數(shù)資料
| 型號： | 908E621 |
| 廠商： | 飛思卡爾半導體(中國)有限公司 |
| 英文描述： | Integrated Quad Half-Bridge and Triple High-Side with Embedded MCU and LIN for High End Mirror |
| 中文描述： | 綜合四半橋和三高的嵌入式微控制器和LIN高端側鏡 |
| 文件頁數(shù)： | 46/62頁 |
| 文件大?。?/td> | 540K |
| 代理商： | 908E621 |
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Analog Integrated Circuit Device Data
Freescale Semiconductor
46
908E621
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
LOGIC COMMANDS AND REGISTERS
908E621 SERIAL PHERIPHERAL INTERFACE (SPI)
The Serial Peripheral Interface (SPI) creates the
communication link between the MCU and the analog die.
The interface consists of four terminals
MOSI - Master Out Slave In (internal pull-down)
MISO - Master In Slave Out
SPSCK - Serial Clock (internal pull-down)
SS - Slave Select (internal pull-up)
A complete data transfer via the SPI, consists of 2 bytes.
The master sends address and data, the slave returns
system status and the data of the selected address.
Figure 29. SPI Protocol
During the inactive phase of SS, the new data transfer will
be prepared. The falling edge on the SS line, indicates
the start of a new data transfer (framing) and puts MISO
in the low impedance mode. The first valid data are
moved to MISO with the rising edge of SPSCK.
The MOSI, MISO will change data on a rising edge of
SPSCK.
The MOSI, MISO will be sampled on a falling edge of
SPSCK.
The data transfer is only valid, if exactly 16 sample clock
edges are present in the active phase of SS.
After a write operation the transmitted data will be latched
into the register, by the rising edge of SS.
Register read data is internally latched into the SPI, at the
time when the parity bit is transferred
SS high will force MISO to high impedance
Master Address Byte
A4 - A0
include the address of the desired register.
R/W
includes the information if it is a read or a write operation.
If R/W = 1 (read operation), second byte of master
contains no valid information, slave just transmits back
register data.
If R/W = 0 (write operation), master sends data to be
written in the second byte, slave sends concurrently
contents of selected register prior to write operation,
write data is latched in the
SmartMOS
registers on
rising edge of SS
Parity P
completes the total number of 1 bits of (R/W,A[4-0]) to an
even number. e.g. (R/W,A[4-0]) = 100001 -> P0 = 0.
The parity bit is only evaluated during a write operations
and ignored for read operations.
Bit X
not used
S7
S6
S5
S4
S3
S2
S1
S0
R/W
A4
A3
A2
A1
A0
P
X
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
System Status Register
Read/Write, Address, Parity
Data (Register write)
Data (Register read)
Rising edge of SPSCK
Change MISO/MOSI
Output
Falling edge of SPSCK
Sample MISO/MOSI
Input
Slave latch
register address
Slave latch
data
SS
MOSI
MISO
SPSCK
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