參數(shù)資料
型號: 89HPES8T5AZBBCGI
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 總線控制器
英文描述: PCI BUS CONTROLLER, PBGA196
封裝: 15 X 15 MM, 1 MM PITCH, GREEN, CABGA-196
文件頁數(shù): 28/29頁
文件大小: 622K
代理商: 89HPES8T5AZBBCGI
8 of 29
May 7, 2009
IDT 89HPES8T5A Data Sheet
Pin Characteristics
Note: Some input pads of the PES8T5A do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate
levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left
floating can cause a slight increase in power consumption.
Function
Pin Name
Type
Buffer
I/O
Type
Internal
Resistor
Notes
PCI Express Inter-
face
PE0RN[1:0]
I
CML
Serial Link
PE0RP[1:0]
I
PE0TN[1:0]
O
PE0TP[1:0]
O
PE2RN[0]
I
PE2RP[0]
I
PE2TN[0]
O
PE2TP[0]
O
PE3RN[0]
I
PE3RP[0]
I
PE3TN[0]
O
PE3TP[0]
O
PE4RN[0]
I
PE4RP[0]
I
PE4TN[0]
O
PE4TP[0]
O
PE5RN[0]
I
PE5RP[0]
I
PE5TN[0]
O
PE5TP[0]
O
PEREFCLKN
I
LVPECL/
CML
Diff. Clock
Input
Refer toTable 9
PEREFCLKP
I
REFCLKM
I
LVTTL
Input
pull-down
SMBus
MSMBADDR[4:1]
I
LVTTL
Input
pull-up
MSMBCLK
I/O
STI1
MSMBDAT
I/O
STI
SSMBADDR[5,3:1]
I
Input
pull-up
SSMBCLK
I/O
STI
SSMBDAT
I/O
STI
General Purpose I/O
GPIO[10:0]
I/O
LVTTL
High Drive
pull-up
Table 8 Pin Characteristics (Part 1 of 2)
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