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參數資料
| 型號： | 89HPES8T5AZBBCGI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA196 |
| 封裝： | 15 X 15 MM, 1 MM PITCH, GREEN, CABGA-196 |
| 文件頁數： | 24/29頁 |
| 文件大?。?/td> | 622K |
| 代理商： | 89HPES8T5AZBBCGI |
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May 7, 2009
IDT 89HPES8T5A Data Sheet
General Purpose Input/Output
The PES8T5A provides 11 General Purpose Input/Output (GPIO) pins that may be used by the system designer as bit I/O ports. Each GPIO pin
may be configured independently as an input or output through software control. Some GPIO pins are shared with other on-chip functions. These
alternate functions may be enabled via software, SMBus slave interface, or serial configuration EEPROM.
Pin Description
The following tables lists the functions of the pins provided on the PES8T5A. Some of the functions listed may be multiplexed onto the same pin.
The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low)
level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.
Signal
Type
Name/Description
PE0RP[3:0]
PE0RN[3:0]
I
PCI Express Port 0 Serial Data Receive. Differential PCI Express receive
pairs for port 0.
PE0TP[3:0]
PE0TN[3:0]
O
PCI Express Port 0 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 0.
PE2RP[0]
PE2RN[0]
I
PCI Express Port 2 Serial Data Receive. Differential PCI Express receive
pair for port 2.
PE2TP[0]
PE2TN[0]
O
PCI Express Port 2 Serial Data Transmit. Differential PCI Express trans-
mit pair for port 2.
PE3RP[0]
PE3RN[0]
I
PCI Express Port 3 Serial Data Receive. Differential PCI Express receive
pair for port 3.
PE3TP[0]
PE3TN[0]
O
PCI Express Port 3 Serial Data Transmit. Differential PCI Express trans-
mit pair for port 3.
PE4RP[0]
PE4RN[0]
I
PCI Express Port 4 Serial Data Receive. Differential PCI Express receive
pair for port 4.
PE4TP[0]
PE4TN[0]
O
PCI Express Port 4 Serial Data Transmit. Differential PCI Express trans-
mit pair for port 4.
PE5RP[0]
PE5RN[0]
I
PCI Express Port 5 Serial Data Receive. Differential PCI Express receive
pair for port 5.
PE5TP[0]
PE5TN[0]
O
PCI Express Port 5 Serial Data Transmit. Differential PCI Express trans-
mit pair for port 5.
PEREFCLKP
PEREFCLKN
I
PCI Express Reference Clock. Differential reference clock pair input. This
clock is used as the reference clock by on-chip PLLs to generate the clocks
required for the system logic and on-chip SerDes. The frequency of the dif-
ferential reference clock is determined by the REFCLKM signal.
REFCLKM
I
PCI Express Reference Clock Mode Select. This signal selects the fre-
quency of the reference clock input.
0x0 - 100 MHz
0x1 - 125 MHz
Table 2 PCI Express Interface Pins
相關PDF資料 |
PDF描述 |
|---|---|
| 89HPES8T5AZBBCI | PCI BUS CONTROLLER, PBGA196 |
| 89HPES8T5AZBBC | PCI BUS CONTROLLER, PBGA196 |
| 89RW30 | SCR |
| 89RW40 | SCR |
| 8AF4NLV | 50 A, 400 V, SILICON, RECTIFIER DIODE |
相關代理商/技術參數 |
參數描述 |
|---|---|
| 89HPES8T5AZBBCGI8 | 制造商:Integrated Device Technology Inc 功能描述:PCI Express Switch I/O Expansion Switch 8Lanes 5Ports 1-CH 196-Pin CABGA 制造商:Integrated Device Technology Inc 功能描述:8-LANE 5-PORT PCI EXPRESS? SWITCH - Tape and Reel |
| 89HPES8T5AZBBCI | 制造商:Integrated Device Technology Inc 功能描述:PCI Express Switch I/O Expansion Switch 8Lanes 5Ports 1-CH 196-Pin CABGA 制造商:Integrated Device Technology Inc 功能描述:PCI EXPRESS SWIT 196CABGA - Rail/Tube |
| 89HPES8T5AZBBCI8 | 制造商:Integrated Device Technology Inc 功能描述:PCI Express Switch I/O Expansion Switch 8Lanes 5Ports 1-CH 196-Pin CABGA 制造商:Integrated Device Technology Inc 功能描述:PCI EXPRESS SWIT 196CABGA - Tape and Reel |
| 89HPES8T5ZBBC | 制造商:Integrated Device Technology Inc 功能描述:8-LANE 5-PORT PCI EXPRESS SWIT 324CABGA - Trays |
| 89HPES8T5ZBBCG | 制造商:Integrated Device Technology Inc 功能描述:8-LANE 5-PORT PCI EXPRESS SWIT 324CABGA - Trays |
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