參數(shù)資料
型號： 89HPES8T5AZBBCGI
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA196
封裝： 15 X 15 MM, 1 MM PITCH, GREEN, CABGA-196
文件頁數(shù)： 12/29頁
文件大?。?/td> 622K
代理商： 89HPES8T5AZBBCGI
2 of 29
May 7, 2009
IDT 89HPES8T5A Data Sheet
◆
11 General Purpose Input/Output Pins
– Each pin may be individually configured as an input or output
– Each pin may be individually configured as an interrupt input
– Some pins have selectable alternate functions
◆
Packaged in a 15mm x 15mm 196-ball BGA with 1mm ball spacing
Product Description
Utilizing standard PCI Express interconnect, the PES8T5A provides the most efficient I/O connectivity solution for applications requiring high
throughput, low latency, and simple board layout with a minimum number of board layers. It provides 3 GBps (24 Gbps) of aggregated, full-duplex
switching capacity through 6 integrated serial lanes, using proven and robust IDT technology. Each lane provides 2.5 Gbps of bandwidth in both direc-
tions and is fully compliant with PCI Express Base specification revision 1.1.
The PES8T5A is based on a flexible and efficient layered architecture. The PCI Express layer consists of SerDes, Physical, Data Link and Trans-
action layers in compliance with PCI Express Base specification Revision 1.1. The PES8T5A can operate either as a store and forward or cut-through
switch and is designed to switch memory and I/O transactions. It supports eight Traffic Classes (TCs) and one Virtual Channel (VC) with sophisticated
resource management to allow efficient switching for applications requiring additional narrow port connectivity.
Figure 2 I/O Expansion Application
SMBus Interface
The PES8T5A contains two SMBus interfaces. The slave interface provides full access to the configuration registers in the PES8T5A, allowing
every configuration register in the device to be read or written by an external agent. The master interface allows the default configuration register
values of the PES8T5A to be overridden following a reset with values programmed in an external serial EEPROM. The master interface is also used
by an external Hot-Plug I/O expander.
Six pins make up each of the two SMBus interfaces. These pins consist of an SMBus clock pin, an SMBus data pin, and 4 SMBus address pins. In
the slave interface, these address pins allow the SMBus address to which the device responds to be configured. In the master interface, these
address pins allow the SMBus address of the serial configuration EEPROM from which data is loaded to be configured. The SMBus address is set up
on negation of PERSTN by sampling the corresponding address pins. When the pins are sampled, the resulting address is assigned as shown in
Memory
Processor
Memory
North
Bridge
PES8T5A
Processor
x1
South
Bridge
GE
LOM
x4
GE
LOM
GE
1394
相關(guān)PDF資料
PDF描述
89HPES8T5AZBBCI PCI BUS CONTROLLER, PBGA196
89HPES8T5AZBBC PCI BUS CONTROLLER, PBGA196
89RW30 SCR
89RW40 SCR
8AF4NLV 50 A, 400 V, SILICON, RECTIFIER DIODE
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
89HPES8T5AZBBCGI8 制造商:Integrated Device Technology Inc 功能描述:PCI Express Switch I/O Expansion Switch 8Lanes 5Ports 1-CH 196-Pin CABGA 制造商:Integrated Device Technology Inc 功能描述:8-LANE 5-PORT PCI EXPRESS? SWITCH - Tape and Reel
89HPES8T5AZBBCI 制造商:Integrated Device Technology Inc 功能描述:PCI Express Switch I/O Expansion Switch 8Lanes 5Ports 1-CH 196-Pin CABGA 制造商:Integrated Device Technology Inc 功能描述:PCI EXPRESS SWIT 196CABGA - Rail/Tube
89HPES8T5AZBBCI8 制造商:Integrated Device Technology Inc 功能描述:PCI Express Switch I/O Expansion Switch 8Lanes 5Ports 1-CH 196-Pin CABGA 制造商:Integrated Device Technology Inc 功能描述:PCI EXPRESS SWIT 196CABGA - Tape and Reel
89HPES8T5ZBBC 制造商:Integrated Device Technology Inc 功能描述:8-LANE 5-PORT PCI EXPRESS SWIT 324CABGA - Trays
89HPES8T5ZBBCG 制造商:Integrated Device Technology Inc 功能描述:8-LANE 5-PORT PCI EXPRESS SWIT 324CABGA - Trays
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*