- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄223059 > 843002AKI-40LF (INTEGRATED DEVICE TECHNOLOGY INC) 175 MHz, OTHER CLOCK GENERATOR, QCC32 PDF資料下載
參數(shù)資料
| 型號： | 843002AKI-40LF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | XO, clock |
| 英文描述： | 175 MHz, OTHER CLOCK GENERATOR, QCC32 |
| 封裝： | 3 X 3 MM, 0.95 MM HEIGHT, ROHS COMPLIANT, MO-220VHHD, VFQFN-32 |
| 文件頁數(shù)： | 8/24頁 |
| 文件大?。?/td> | 742K |
| 代理商： | 843002AKI-40LF |
ICS843002I-40
175MHZ, FEMTOCLOCKS VCXO BASED SONET/SDH JITTER ATTENUATOR
IDT / ICS VCXO BASED SONET/SDH JITTER ATTENUATOR
16
ICS843002AKI-40 REV. B APRIL 27, 2009
Schematic Example
Figure 7 shows a schematic example of the ICS843002I-40
application schematic. In this example, the device is operated at
VCC = 3.3V. The decoupling capacitors should be located as close
as possible to the power pin. The input is driven by a 3.3V LVPECL
driver. The 2-pole filter example is used in this schematic. Please
refer to the ICS843002I-40 datasheet for additional loop filter
recommendations.
Figure 7. ICS843002I-40 Schematic Example
Loss of Reference Indicator (LOR0 and LOR1) Output Pins
The LOR0 and LOR1 pins are controlled by the internal clock
activity monitor circuits. The clock activity monitor circuits are
clocked by the VCXO PLL phase detector feedback clock. The
LOR output is asserted high if there are three consecutive
feedback clock edges without any reference clock edges (in both
cases, either a negative or positive transition is counted as an
“edge”). The LOR output will otherwise be low. In a phase detector
observation interval, the activity monitor does not flag excessive
reference transitions as an error. The monitor only distinguishes
between transitions occurring and no transitions occurring.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 84364-5 | 22 CONTACT(S), FEMALE, STRAIGHT TWO PART BOARD CONNECTOR, SURFACE MOUNT, RECEPTACLE |
| 84364-7 | 12 CONTACT(S), FEMALE, STRAIGHT TWO PART BOARD CONNECTOR, SURFACE MOUNT, RECEPTACLE |
| 84364-8 | 12 CONTACT(S), FEMALE, STRAIGHT TWO PART BOARD CONNECTOR, SURFACE MOUNT, RECEPTACLE |
| 84364-9 | 34 CONTACT(S), FEMALE, STRAIGHT TWO PART BOARD CONNECTOR, SURFACE MOUNT, RECEPTACLE |
| 844256BGT | 622.08 MHz, OTHER CLOCK GENERATOR, PDSO24 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 843002AKI-40LFT | 功能描述:時(shí)鐘合成器/抖動清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| 843002AKI-40T | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:175MHZ, FEMTOCLOCKTM VCXO BASED SONET/SDH JITTER ATTENUATOR |
| 843002AKI-41 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:700MHZ, FEMTOCLOCKTM VCXO BASED SONET/SDH JITTER ATTENUATOR |
| 843002AKI-41LF | 功能描述:時(shí)鐘合成器/抖動清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| 843002AKI-41LFT | 制造商:Integrated Device Technology Inc 功能描述:PLL Clock Generator Dual 32-Pin VFQFPN EP T/R 制造商:Integrated Device Technology Inc 功能描述:PLL CLOCK GEN DUAL 32PIN VFQFPN - Tape and Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。