參數(shù)資料
型號： 843002AKI-40LF
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： XO, clock
英文描述： 175 MHz, OTHER CLOCK GENERATOR, QCC32
封裝： 3 X 3 MM, 0.95 MM HEIGHT, ROHS COMPLIANT, MO-220VHHD, VFQFN-32
文件頁數(shù)： 18/24頁
文件大?。?/td> 742K
代理商： 843002AKI-40LF
ICS843002I-40
175MHZ, FEMTOCLOCKS VCXO BASED SONET/SDH JITTER ATTENUATOR
IDT / ICS VCXO BASED SONET/SDH JITTER ATTENUATOR
3
ICS843002AKI-40 REV. B APRIL 27, 2009
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Number
Name
Type
Description
1, 2
LF1, LF0
Analog
Input/Output
Loop filter connection node pins.
3
ISET
Analog
Input/Output
Charge pump current setting pin.
4VCC
Power
Core power supply pin.
5
CLK0
Input
Pulldown
Non-inverting differential clock input.
6nCLK0
Input
Pullup
Pulldown
Inverting differential clock input. VCC/2 bias voltage when left floating.
7
CLK_SEL
Input
Pulldown
Input clock select. LVCMOS/LVTTL interface levels. See Table 3A.
8, 11, 22
nc
Unused
No connect.
9,
10
QA_SEL1,
QA_SEL0
Input
Pullup
Output divider control for QA/nQA LVPECL outputs.
LVCMOS/LVTTL interface levels.See Table 3C.
12,
13
QB_SEL1,
QB_SEL0
Input
Pullup
Output divider control for QB/nQB LVPECL outputs.
LVCMOS/LVTTL interface levels.See Table 3C.
14
VCCA
Power
Analog supply pin.
15, 16
QA, nQA
Output
Differential clock output pair. LVPECL interface levels.
17, 27
VEE
Power
Negative supply pins.
18, 19
QB, nQB
Output
Differential clock output pair. LVPECL interface levels.
20
VCCO_LVPECL
Power
Output supply pin for LVPECL outputs.
21
VCCO_LVCMOS
Power
Output supply pin for LVCMOS/LVTTL outputs.
23
LOR1
Output
Alarm output, loss of reference for CLK1/nCLK1.
LVCMOS/LVTTL interface levels.
24
LOR0
Output
Alarm output, loss of reference for CLK0/nCLK0.
LVCMOS/LVTTL interface levels.
25
nCLK1
Input
Pullup
Pulldown
Inverting differential clock input. VCC/2 bias voltage when left floating.
26
CLK1
Input
Pulldown
Non-inverting differential clock input.
28,
29,
30
R_SEL0,
R_SEL1,
R_SEL2
Input
Pulldown
Input divider selection. LVCMOS/LVTTL interface levels. See Table 3B.
31,
32
XTAL_OUT,
XTAL_IN
Input
Crystal oscillator interface. The XTAL_IN is the input.
XTAL_OUT is the output.
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
CIN
Input Capacitance
4
pF
RPULLUP
Input Pullup Resistor
50
k
RPULLDOWN Input Pulldown Resistor
50
k
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843002AKI-40LFT 功能描述:時鐘合成器/抖動清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
843002AKI-40T 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:175MHZ, FEMTOCLOCKTM VCXO BASED SONET/SDH JITTER ATTENUATOR
843002AKI-41 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:700MHZ, FEMTOCLOCKTM VCXO BASED SONET/SDH JITTER ATTENUATOR
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843002AKI-41LFT 制造商:Integrated Device Technology Inc 功能描述:PLL Clock Generator Dual 32-Pin VFQFPN EP T/R 制造商:Integrated Device Technology Inc 功能描述:PLL CLOCK GEN DUAL 32PIN VFQFPN - Tape and Reel
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