參數(shù)資料
型號(hào)： 82803AAMRH-R
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁(yè)數(shù)： 39/52頁(yè)
文件大小： 322K
代理商： 82803AAMRH-R
82803AA MRH-R
R
Datasheet
39
Bus Timings
The SMBus runs at between 10-80 KHz. Most of the timings associated with the SMBus are
microseconds in length. SMBCLK is generated by dividing ExSCK by 16. Thus, when ExSCK is 1 MHz
SMBCLK is 62.5 KHz.
Bus Time Out
If there is an error in the transaction, such that EEPROM does not signal an acknowledge, or holds the
clock lower than the allowed time-out time, the transaction times out. The MRH-R discards the cycle,
and sets bit 14 of the SPDRDR register to indicate the error. The time out minimum is 25 ms. The time-
out counter inside the MRH-R starts after the last bit of data is transferred by the MRH-R and it is
waiting for a response.
4.2.
Reset
After assertion of the MRH-R’s RST# input, all internal configuration registers are reset to their default
states. The ‘expansion’ and ‘stick’ channel RACs are forced to a powered down state and remain there
until a RAC initialization command is issued via the CMOS serial bus. All DRCGs are disabled and
powered down. RST# should not be deasserted until the ‘expansion’ channel clocks are running stable.
RST# should be prevented from being asserted during a system STR resume sequence to allow the
MRH-R internal registers to be preserved. This allows serial channel device ID setup and RSL
levelization phases in the Initialization sequence to be skipped, preventing any read or write accesses to
RDRAM devices with valid data.
4.3.
Power Management
There are two bits specified in EXCC register (Offset 02h) to turn off the logic associated with a ‘stick’
channel A/B when there are no devices connected to specified ‘stick’ channel.
4.4.
STR Support
The 82803AA MRH-R should be powered down and it’s registers saved to memory when supporting the
S3, suspend to RAM, sleep state.
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