參數(shù)資料
型號(hào): 82803AAMRH-R
英文描述: Controller Miscellaneous - Datasheet Reference
中文描述: 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁(yè)數(shù): 21/52頁(yè)
文件大?。?/td> 322K
代理商: 82803AAMRH-R
82803AA MRH-R
R
Datasheet
21
Bit
Description
14:12
Levelization Commands (LCMD).
000 =
NOP.
no command.
001 =
Write to tCAC field (W_TCAC).
write-enables the tCAC field (bits 11:8) in this register.
010 =
Write to tRDLY field (W_TRDLY).
write-enable for tRDLY field (bits 6:4). This field can be
written to in levelization or non-levelization mode. However, while in levelization mode, the value
contained in this register will NOT affect ‘stick’ channel read delay towards the ‘expansion’
channel.
011 =
Write to tRDLY_stick field (W_STRDLY).
tRDLY_stick field (bits 2:0) are written. In this case,
the measured value during levelization is overwritten. If the MRH-R is in levelization mode, then
this command has no effect.
100 =
Write to clock frequency bit (W_FREQ).
The MCH writes to Bit 7 of this register before RAC
initialization to determine the RDRAM Clock Frequency for the MRH-R.
101 =
Write ALL Fields (W_ALL).
Causes all fields (tCAC, tRDLY, tRDLY_stick, and frequency) to be
written to. Can be used for R/W testing of the register bits. Note that the tRDLY_stick field write
restriction still applies while in levelization mode.
110 =
Clear Levelization Mode (CLM).
Causes the MRH-R to exit levelization mode. The last
measured read data delay value during levelization - the tCAC value in bits 11:8 of this register
will be contained in the tRDLY_stick bits. During normal mode, the value of the tRDLY register
will now also affect the delay in the MRH-R read FIFO unload to the ‘expansion’ bus (which
effectively delays read data towards the MCH).
111 =
Set Levelization Mode (SLM).
This command causes the MRH-R to enter levelization mode.
In this mode, read data delay from the ‘stick’ channels to the ‘expansion’ channel remains fixed
at 3 rclks – tTR, regardless of the value in the MRH-R tRDLY register and the tRDLY_stick field
of this register. The MRH-R also starts measuring (on-the-fly), the # rclks from an expansion
SCP read command to when a leading ‘1’ bit is detected in the internal read path from either
‘stick’ channel on ‘stick’ channel data signal DQA5, or in other words, the ‘stick’ channel’s read
delay. The desired read to be measured is to the last (furthest) RDRAM on the ‘stick’ channel.
11:8
RDRAM tCAC read access delay (tCAC).
(Write-gated by W_TCAC above). This field defines the
minimum delay in rclks for RDRAMs from a Read SCP command to read data on the ‘stick’ channels
(4-9). Values of 0-3, and A-Fh are illegal. The MRH-R must use this parameter to time its read data
path.
7
RDRAM Clock Frequency (freq).
(Write-gated by W_FREQ above]. Must be set to proper value
before RAC initialization begins.
0 = 300 MHz bus operation
1 = 400 MHz bus operation.
6:4
Expansion Channel Time Domains (tRDLY).
[Write-gated by W_TRDLY above]. This field controls
the read data delay from the MRH-R to the ‘expansion’ channel. Its purpose is to allow time domain
equalization to be achieved among ALL ‘stick’ channels behind ALL MRH-Rs to the MCH. During
levelization, the value of this register will not affect read data delay thru the MRH-R which remains
fixed at 3-tTR rclks. In normal operation, its value will add to the total read data delay from all RDRAM
devices on the MRH-R’s ‘stick’ channels to the MCH. It is written to using the W_TRDLY command
(see above) via a CMOS serial write to this register.
3
Reserved
2:0
Stick Channel Time Domains (tRDLY_stick).
(Write-gated by W_STRDLY above). This field is
written to by the MRH-R itself while in levelization mode with a measured delay (0-7 rclks) from a
‘stick’ channel SCP read packet to the first non-zero data seen on ‘stick’ channel signal DQA5 at the
MRH-R ‘stick’ channel interfaces. It is used internally by the MRH-R primarily to control its read data
delay FIFO loading and to control the ‘stick’ channels to ‘expansion’ channel data steering mux. It can
also be written to using a W_STRDLY command (see above) via a CMOS serial write to this register,
but while the MRH-R is in levelization mode, it is Read-Only (ie. wrt CMOS bus). BIOS can read this
field to determine the number of time domains on the addressed MRH-R’s ‘stick’ channels.
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